TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
36
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vector table mapping
The interrupt vector table can be mapped into the five distinct areas listed in Table 19.
Table 19. Interrupt Vector Table Mapping
†
VECTOR MAPS
VECTORS FETCHED
FROM
ADDRESS RANGE VMAP M0M1MAP MP/MC ENPIE
M1 Vector
‡
M1 SARAM Block 0x000000–0x00003F 0 0 X X
M0 Vector M0 SARAM Block 0x000000–0x00003F 0 1 X X
BROM Vector ROM Block 0x3FFFC0–0x3FFFFF 1 X 0 0
XINTF Vector
§
XINTF Zone 7 Block 0x3FFFC0–0x3FFFFF 1 X 1 0
PIE Vector PIE Block 0x000D00–0x000DFF 1 X X 1
†
On the F2810 and F2812 devices, the VMAP and M0M1MAP modes are set to “1” on reset. The ENPIE mode is forced to “0” on reset.
‡
Vector map M1 Vector is a reserved mode only.
§
Valid on F2812 only
After reset operation, the vector table will be located in the areas listed in Table 20.
Table 20. Vector Table Mapping After Reset Operation
†
VECTOR MAPS
RESET FETCHED
FROM
ADDRESS RANGE VMAP M0M1MAP MP/MC ENPIE
BROM Vector ROM Block 0x3FFFC0–0x3FFFFF 1 1 0 0
XINTF Vector
§
XINTF Zone 7 Block 0x3FFFC0–0x3FFFFF 1 1 1 0
†
On the F2810 and F2812 devices, the VMAP and M0M1MAP modes are set to “1” on reset. The ENPIE mode is forced to “0” on reset.
§
Valid on F2812 only
The vector mapping is controlled by the following mode bits/signals:
VMAP: This bit is found in Status Register 1 (bit 3). A device reset sets this bit to 1. The state of this
bit can be modified by writing to ST1 or by “SETC/CLRC VMAP” instructions.
M0M1MAP: This bit is found in Status Register 1 (bit 11). A device reset sets this bit to 1. The state of this
bit can be modified by writing to ST1 or by “SETC/CLRC M0M1MAP” instructions. This bit
should remain set. M0M1MAP = 0 is reserved for TI testing.
MP/MC
: This bit is found in XINTCNF2 Register (bit 8). On the F2812, the default value of this bit, on
reset, is set by the XMP/MC
input device signal. On the F2810, XMP/MC is tied low internally.
The state of this bit can be modified by writing to the XINTCNF2 register (address 0x0000
0B34).
ENPIE: This bit is found in PIECTRL Register (bit 0). The default value of this bit, on reset, is set to “0”
(PIE disabled). The state of this bit can be modified by writing to the PIECTRL register
(address 0x0000 0CE0).
The external interrupts are configured using the registers listed in Table 27.
PR
DU
T PREVIEW
