TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

XINTCNF2 register

Table 15. XINTCNF2 Register Bit Definitions

BITS TYPE NAME RESET DESCRIPTION

1,0 R/W Write

Buffer

Depth

0,0 The write buffer allows the processor to continue execution without waiting for

XINTF write accesses to complete. The write buffer depth is selectable as follows:

Depth Action

00 No write buffering. The CPU will be stalled until the write

completes on the XINTF.

Note: Default mode on reset (XRS

01 The XINTF will buffer one word. The CPU is stalled until the

write cycle begins on the XINTF (there could be a read cycle

currently active on the XINTF).

10 One write will be buffered without stalling the CPU. The CPU

is stalled if a second write follows. The CPU will be stalled

until the first write begins its cycle on the XINTF.

11 Two writes will be buffered without stalling the CPU. The CPU

is stalled if a third write follows. The CPU will be stalled until

the first write begins its cycle on the XINTF.

The buffered access can be 8, 16, or 32 bits in length. Order of execution is

preserved, e.g., writes are performed in the order they were accepted. The

processor is stalled on XINTF reads until all pending writes are done and the read

access completes. If the buffer is full, any pending reads or writes to the buffer

will stall the processor.

The “Write Buffer Depth” can be changed; however, it is recommended that the

write buffer depth be changed only when the buffer is empty (this can be checked

by reading the “Write Buffer Level” bits). Writing to these bits when the level is not

zero may have unpredictable results.

2 R/W CLKMODE

Mode

1 XCLKOUT divide by 2 mode. If this bit is set to 1, XCLKOUT is a divide by 2 of

XTIMCLK. If this bit is set to 0, XCLKOUT is equal to XTIMCLK. All bus timings,

irrespective of which mode is enabled, will start from the rising edge of XCLKOUT.

The default mode of operation on power up and reset is /2 mode.

3 R/W CLKOFF 0 Turn XCLKOUT off mode. When this bit is set to 1, the XCLKOUT signal is turned

off. This is done for power savings and noise reduction. This bit is set to 0 on a

reset.

4 R Reserved 1 Reserved

5 R Reserved 0 Reserved

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

XINTCNF2 register (continued)

Table 15. XINTCNF2 Register Bit Definitions (Continued)

BITS TYPE NAME RESET DESCRIPTION

7,6 R WLEVEL 0,0 The current number of writes buffered are detectable as follows:

Level Action

00 empty

01 1 value currently in the write buffer

10 2 values currently in the write buffer

11 3 values currently in the write buffer

The value in the write buffer may be 8-, 16-, or 32-bit data.

Note: There may be a few cycle delay from when a value enters the write buffer

to the buffer level depth being updated.

8 R/W MP/MC

Mode

On reset, this bit reflects the state of the XMP/MC input signal sampled at XRS.

The user can modify the state of this bit by writing a 1 or a 0 to this location. This

will be reflected on the XMP/MC output signal. This mode also affects ZONE 7 and

Boot ROM mapping as follows:

MP/MC

= 1, microprocessor state

(XINTF ZONE 7 enabled, Boot ROM disabled).

MP/MC

= 0, microcomputer state

(XINTF ZONE 7 disabled, Boot ROM enabled).

Note: The XMP/MC

input signal state is ignored after reset.

9 R/W HOLD 0 This bit, when low, will automatically grant a request to an external device driving

the XHOLD

input signal low (XHOLDA output signal is driven low when request

granted). This bit, when set high, will not automatically grant a request to an

external device driving the XHOLD input signal low (XHOLDA output signal stays

high).

If this bit is set, while XHOLD

and XHOLDA are both low (external bus accesses

granted) then the XHOLDA

signal is forced high (at the end of the current cycle)

and the exteranl interface is taken out of high-impedance mode.

On a reset XRS

, this bit is set to zero. If on a reset the XHOLD signal is active-low,

then the bus and all signal strobes must be in high-impedance state and the

XHOLDA

signal also driven active-low.

When HOLD mode is enabled and XHOLDA is active-low (external bus grant

active) then the core can still execute code from internal memory. If an access is

made to the external interface, then a not ready signal is generated and the core

is stalled until the XHOLD

signal is removed.

10 R HOLDS XHOLD input

signal

This bit reflects the current state of the XHOLD input signal. It can be read by the

user to determine if an external device is requesting access to the external bus.

11 R HOLDAS XHOLDA input

signal

This bit reflects the current state of the XHOLDA output signal. It can be read by

the user to determine if the external interface is currently granting access to an

external device.

T PREVIEW

TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

XINTCNF2 register (continued)

Table 15. XINTCNF2 Register Bit Definitions (Continued)

BITS TYPE NAME RESET DESCRIPTION

15:12 X Reserved 0 Reserved

18:16 R/W XTIMCLK 0,0,1 These bits select the fundamental clock for the timing of lead, active and trail

switching operations as defined by the XTIMING and XBANK registers:

Mode Action

0,0,0 XTIMCLK = SYSCLKOUT/1

0,0,1 XTIMCLK = SYSCLKOUT/2

0,1,0 reserved

0,1,1 reserved

1,0,0 reserved

1,0,1 reserved

1,1,0 reserved

1,1,1 reserved

XBANK register

Table 16. XBANK Register Bit Defintions

BITS TYPE NAME RESET DESCRIPTION

2:0 R/W BANK 1,1,1 These bits specify the XINTF zone for which bank switching is enabled, ZONE

0 to ZONE 7. At reset, XINTF Zone 7 is selected.

5:3 R/W BCYC 1,1,1 These bits specify the number of XTIMCLK cycles to add between any

consecutive access that crosses into or out of the specified zone, be it a read or

write, program or data space. The number of XTIMCLK cycles can be 0 to 14.

On a reset (XRS

) the value defaults to 14 cycles.

14:6 X Reserved

15 R/W Reserved 1

XREVISION register

The XREVISION register contains a unique number to identify the particular version of XINTF used in the

product. For the F2812, this register will be configured as described in Table 17.

Table 17. XREVISION Register Bit Defintions

BIT(S) NAME TYPE RESET DESCRIPTION

15–0 REVISION R 0x0004 Current XINTF Revision. For internal use/reference. Test purposes only. Subject to

change.

T PREVIEW

Part #	TMS320F2812PGFS
Description	MIXED-SIGNAL 28X DSPS EXTENDED TEMP
Category	IC
Availability	Out of Stock
Qty	0

TMS320F2812PGFS

Related Items

Technical Document