TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram
M0 SARAM
1K x 16
CPU-TIMER 0
CPU-TIMER 1
INT[12:1]
CLKIN
Real-Time JTAG
CPU-TIMER 2
Peripheral
Bus
C28x CPU
H0 SARAM
8K × 16
L0 SARAM
4K x 16
INT14
NMI
INT13
Memory Bus
M1 SARAM
1K x 16
Flash
128K x 16 (F2812)
64K x 16 (F2810)
Boot ROM
4K × 16
eCAN
SCIA/SCIB
12-Bit ADC
External Interrupt
Control
(XINT1/2/13, XNMI)
EVA/EVB
Memory Bus
OTP
2K x 16
McBSP
System Control
(Oscillator and PLL
+
Peripheral Clocking
+
Low-Power
Modes
+
WatchDog)
FIFO
FIFO
PIE
(96 interrupts)
†
RS
SPI FIFO
TINT0
TINT1
TINT2
Control
Address(19)
Data(16)
External
Interface
(XINTF)
‡
16 Channels
†
45 of the possible 96 interrupts are used on F2810/F2812.
‡
XINTF is not available on the F2810.
GPIO Pins
XRS
X1/XCLKIN
X2
XPPLDIS
Protected by the Code Security Module.
XINT13
G
P
I
O
M
U
X
L1 SARAM
4K x 16
XNMI
PR
DU
T PREVIEW
