TMS320C203, TMS320C209, TMS320LC203
DIGITAL SIGNAL PROCESSORS
SPRS025B – JUNE 1995 – REVISED AUGUST 1998
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Based Upon the T320C2xLP Core CPU
16-Bit Fixed-Point DSP Architecture
– Six Internal Buses for Increased
Parallelism and Performance
– 32-Bit ALU/Accumulator
– 16 × 16-Bit Single-Cycle Multiplier With a
32-Bit Product
– Block Moves for Data, Program,
I/O Space
– Hardware Repeat Instruction
Instruction Cycle Time
’C203 ’LC203 ’C209
50 ns @ 5 V 50 ns @ 3.3 V 50 ns @ 5 V
35 ns @ 5 V 35 ns @ 5 V
25 ns @ 5 V
Source Code Compatible With TMS320C25
Upwardly Code-Compatible With
TMS320C5x Devices
Four External Interrupts
Boot-Loader Option (’C203 Only)
TMS320C2xx Integrated Memory:
– 544 × 16 Words of On-Chip Dual-Access
Data RAM
– 4K × 16 Words of On-Chip Single-Access
Program/Data RAM (’C209 only)
– 4K × 16 Words of On-Chip Program ROM
(’C209 Only)
224K × 16-Bit Total Addressable External
Memory Space
– 64K Program
– 64K Data
– 64K I/O
– 32K Global
TMS320C2xx Peripherals:
– PLL With Various Clock Options
– ×1, ×2, ×4, 2 (’C203)
– ×2, 2 (’C209)
– On-Chip Oscillator
– One Wait State Software-Programmable
to Each Space (’C209 Only)
– 0 – 7 Wait States Software-Programmable
to Each Space (’C203 Only)
– Six General-Purpose I/O Pins
– On-Chip 20-Bit Timer
– Full-Duplex Asynchronous Serial Port
(UART) (’C203 Only)
– One Synchronous Serial Port With
Four-Level-Deep FIFOs (’C203 Only)
Supports Hardware Wait States
Designed for Low-Power Consumption
– Fully Static CMOS Technology
– Power-Down IDLE Mode
1.1 mA/MIPS at 3.3 V
’C203 is Pin-Compatible With TMS320F206
Flash DSP
Up to 40-MIPS Performance at 5 V (’C203)
20-MIPS Performance at 3.3 V
HOLD Mode for Multiprocessor
Applications
IEEE-1149.1
†
-Compatible Scan-Based
Emulation
80- and 100-pin Small Thin Quad Flat
Packages (TQFPs), (PN and PZ Suffixes)
description
The TMS320C2xx generation of digital signal processors (DSPs) combines strong performance and great
flexibility to meet the needs of signal processing and control applications. The T320C2xLP core CPU that is the
basis of all ’C2xx devices has been optimized for high speed, small size, and low-power, making it ideal for
demanding applications in many markets. The CPU has an advanced, modified Harvard architecture with six
internal buses that permits tremendous parallelism and data throughput. The powerful ’C2xx instruction set
makes software development easy. And because the ’C2xx is code-compatible with the TMS320C2x and ’C5x
generations, your code investment is preserved. Around this core, ’C2xx-generation devices feature various
combinations of on-chip memory and peripherals. The serial ports provide easy communication with external
devices such as codecs, A/D converters, and other processors. Other peripherals that facilitate the control of
external devices include general-purpose I/O pins, a 20-bit timer, and a wait-state generator.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1998, Texas Instruments Incorporated
†
IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port.
