TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Input protection circuit operation
Texas Instruments patented protection circuitry allows for both positive- and negative-going ESD transients.
These transients are characterized by extremely fast rise times and usually low energies, and can occur both
when the device has all pins open and when it is installed in a circuit.
positive ESD transients
Initial positive charged energy is shunted through Q1 to V
SS
. Q1 turns on when the voltage at the input rises
above the voltage on V
DD
by a value equal to the V
EB
of Q1. The base current increases through R2 with input
current as Q1 saturates. The base current through R2 as Q1 saturates forces the voltage at the drain and gate
of Q2 to exceed its threshold level (V
T
∼ 22 to 26 V) and turn on Q2. The shunted input current through Q1 to
V
SS
is now shunted through the n-channel enhancement-type MOSFET Q2 to V
SS
. If the voltage on the input
pin continues to rise, the breakdown voltage of d3 is exceeded and all remaining energy is dissipated in R1 and
D3. The breakdown voltage of D3 is designed to be 24 V to 27 V, which is well below the gate oxide voltage of
the circuit to be protected.
negative ESD transients
The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1
and D2 as D2 becomes forward-biased. The voltage seen by the protected circuit is –0.3 V to –1 V (the forward
voltage of D1 and D2).
circuit-design considerations
LinCMOS products are being used in actual circuits environments that have input voltages that exceed the
recommended common-mode input voltage range and activate the input protection circuit. Even under normal
operation, these conditions occur during circuit power up or power down, and in many cases, when the device
is being used for a signal conditioning function. The input voltages can exceed V
ICR
and not damage the device
only if the inputs are current limited. The recommended current limit shown on most product data sheets is
±5 mA. Figures 5 and 6 show typical characteristics for input voltage vs input current.
Normal operation and correct output state can be expected even when the input voltage exceeds the positive
supply voltage. The input current should be externally limited even through internal positive current limiting is
achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current
to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input
current. This current is forced into the V
DD
pin and into the device I
DD
or the V
DD
supply through R2 producing
the current limiting effects shown in Figure 5. This internal limiting lasts only as long as the input voltage is below
the V
T
of Q2.
When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage
states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be
severely affected. External current limiting must be used since this current is directly shunted by D1 and D2,
and no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp
is required (see Figure 7).
