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TLC374MFKB

Part # TLC374MFKB
Description Comparator Quad ±8V/16V 20-Pin CLLCC
Category IC
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Texas Instruments
Date Code: 0829
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C NOVEMBER 1983 REVISED MARCH 1999
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
The digital output stage of the TLC374 can be damaged if it is held in the linear region of the transfer curve.
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the
following alternative for measuring parameters such as input offset voltage, common-mode rejection, etc., are
offered.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 1(b) for the V
ICR
test, rather than changing the input voltages, to provide greater
accuracy.
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal, but
opposite in polarity to the input offset voltage, the output changes state.
5 V
5.1 k
(a) V
IO
WITH V
IC
= 0
(b) V
IO
WITH V
IC
= 4 V
Applied V
IO
Limit
V
O
1 V
Applied V
IO
Limit
V
O
5.1 k
4 V
Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C NOVEMBER 1983 REVISED MARCH 1999
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer with C2 and R4 removing any residual
dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input
exactly equals the input offset voltage.
Voltage divider R9 and R10 provide a step up of the input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is
suggested that their tolerance level be 1% or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage
can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from
the measurement obtained with a device in the socket to obtain the actual input current of the device.
+
DUT
+
+
U1b
1/4 TLC274CN
Buffer
C2
1 µF
R1
240 k
U1a
1/4 TLC274CN
Triangle
Generator
R2
10 k
R3
100 k
C1
0.1 µF
R10
100 , 1%
R9
10 k, 1%
R8
1.8 k, 1%
R7
1 M
R6
5.1 k
R5
1.8 k, 1%
C3
0.68 µF
U1c
1/4 TLC274CN
Integrator
C4
0.1 µF
R4
47 k
V
DD
V
IO
(X100)
Figure 2. Test Circuit for Input Offset Voltage Measurement
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C NOVEMBER 1983 REVISED MARCH 1999
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Response time is defined as the interval between the application of an input step function and the instant when the
output reaches 50% of its maximum value. Response time, low-to-high-level output, is measured from the trailing
edge of the input pulse. Response-time measurement at low input signal levels can be greatly affected by the input
offset voltage. The offset voltage should be balanced by the adjustment at the inverting input (as shown in Figure 3)
so that the circuit is just at the transition point. Then a low signal, for example, 105-mV or 5-mV overdrive, causes
the output to change state.
50%
OUT
5.1 k
1 µF
V
DD
Pulse Generator
C
L
(see Note A)
50
1 k
0.1 µF
TEST CIRCUIT
10
10 Turn
1 V
1 V
Input
Offset Voltage
Compensation
Adjustment
VOLTAGE WAVEFORMS
t
PLH
t
r
10%
90%
100 mV
Overdrive
Input
Low-to-High-
Level Output
50%
t
PLH
t
f
10%
90%
100 mV
Overdrive
Input
High-to-Low-
Level Output
NOTE A: C
L
includes probe and jig capacitance.
Figure 3. Response, Rise, and Fall Times Test Circuit and Voltage Waveforms
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