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TL16C552AFN

Part # TL16C552AFN
Description UART 2-CH 16Byte FIFO 5V 68-Pin PLCC Tube - DP1
Category IC
Availability In Stock
Qty 3
Qty Price
1 + $5.46940
Manufacturer Available Qty
Texas Instruments
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
IBM PC/AT Compatible
Two TL16C550 ACEs
Enhanced Bidirectional Printer Port
16-Byte FIFOs Reduce CPU Interrupts
Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation
Transmit, Receive, Line Status, and Data
Set Interrupts on Each Channel
Independently Controlled
Individual Modem Control Signals for Each
Channel
Programmable Serial Interface
Characteristics for Each Channel:
– 5-, 6-, 7-, or 8-Bit Characters
– Even, Odd, or No Parity Bit Generation
and Detection
– 1-, 1-1/2-, or 2-Stop Bit Generation
3-State Outputs Provide TTL Drive for the
Data and Control Bus on Each Channel
Hardware and Software Compatible With
TL16C452
28 29
INT1
INT2
SLIN
INIT
AFD
STB
GND
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
INT0
BDO
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
SOUT1
DTR1
RTS1
CTS1
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
TXRDY0
V
DD
RTS0
DTR0
SOUT0
31 32 33 34
HV or FN PACKAGE
(TOP VIEW)
ACK
PE
87 65493
GND
RI1
DSR1
CLK
CS1
TRI
PEMD
IOW
IOR
CS2
RESET
DCD0
RI0
DSR0
CS0
A2
A1
A0
168672
35 36 37 38 39
66 65
27
GND
CTS0
BUSY
SLCT
64 63 62 61
40 41 42 43
SIN0
TXRDY1
ENIRQ
ERR
SIN1
RXRDY1
RXRDY0
DCD1
V
DD
V
DD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
IBM PC/AT is a trademark of International Business Machines Corporation.
TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
22 23
NC
ENIRQ
TXRDY1
SIN0
V
DD
RESET
CS2
IOR
IOW
A0
A1
A2
CS0
DSR0
RI0
DCD0
CTS0
GND
NC
NC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
NC
RXRDY1
SIN1
ERR
V
DD
SLCT
BUSY
PE
ACK
PEMD
TRI
CS1
CLK
DSR1
RI1
GND
DCD1
RXRDY0
NC
25 26 27 28
PN PACKAGE
(TOP VIEW)
PD2
79 78 77 76 7580 74
INT2
SLIN
INIT
AFD
STB
GND
PD0
DB4
DB6
SOUT1
DTR1
RTS1
CTS1
DB0
DB1
DB2
72 71 7073
29
30 31 32 33
69 68
21
NC
PD4
67 66 65 64
34 35 36 37
DB7
TXRDY0
RTS0
PD5
PD6
PD7
INT0
NC
INT1
DTR0
SOUT0
38 39 40
BDO
NC
63 62 61
PD1
PD3
NC
DB3
NC
DB5
NC
V
DD
description
The TL16C552A is an enhanced dual-channel version of the popular TL16C550B asynchronous
communications element (ACE). The device serves two serial input/output interfaces simultaneously in
microcomputer or microprocessor-based systems. Each channel performs serial-to-parallel conversion on data
characters received from peripheral devices or modems and parallel-to-serial conversion on data characters
transmitted by the CPU. The complete status of each channel of the dual ACE can be read at any time during
functional operation by the CPU. The information obtained includes the type and condition of the transfer
operations being performed and the error conditions encountered.
In addition to its dual communications interface capabilities, the TL16C552A provides the user with a
bidirectional parallel data port that fully supports the parallel Centronics-type printer interface. The parallel port
and the two serial ports provide IBM PC/AT-compatible computers with a single device to serve the three system
ports. A programmable baud rate generator that can divide the timing reference clock input by a divisor between
1 and (2
16
– 1) is included.
The TL16C552A is available in a 68-pin plastic-leaded chip-carrier (FN) package, a 48-pin TQFP (PN) package,
and the 80-pin TQFP (PN) package. The TL16C552AM is available in a 68-pin ceramic quad flat (HV) package.
TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
functional block diagram
CTS0
DSR0
DCD0
RI0
SIN0
CS0
DB0DB7
RTS0
DTR0
SOUT0
INT0
RXRDY0
TXRDY0
RTS1
DTR1
SOUT1
INT1
RXRDY1
TXRDY1
BDO
24
25
26
45
9
22
12
11
10
60
61
42
5346
57
56
55
58
59
CTS1
DSR1
DCD1
RI1
SIN1
CS1
28
31
29
30
41
32
1421
8
8
13
5
8
6
62
3
3533
36
37
39
4
A0A2
IOW
IOR
RESET
CLK
ERR
SLCT
BUSY
PE
ACK
PEMD
CS2
ENIRQ
63
65
66
67
68
1
38
43
8
8
PD0PD7
INIT
AFD
STB
SLIN
INT2
44
Select
and
Control
Logic
Parallel
Port
ACE
#2
ACE
#1
3
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