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TIBPAL22V10ACNT

Part # TIBPAL22V10ACNT
Description 25NS TPD AT 180MA ICC - Rail/Tube
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
13
power-up reset
Following power up, all registers are reset to zero. The output level depends on the polarity selected during
programming. This feature provides extra flexibility to the system designer and is especially valuable in
simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of V
CC
be
monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and
feedback setup times are met.
1.5 V
t
su
t
pd
t
w
V
OL
V
OH
V
IL
V
IH
5 V
V
CC
Active High
Registered Output
Active Low
Registered Output
CLK
4 V
V
OH
V
OL
1.5 V
1.5 V
(600 ns typ, 1000 ns MAX)
State Unknown
1.5 V
State Unknown
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 3. Power-Up Reset Waveforms
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
14
PARAMETER MEASUREMENT INFORMATION
t
su
S1
R2
C
L
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
(3.5 V) [3 V]
(0.3 V) [0]
1.5 V
1.5 V
t
h
1.5 V
t
pd
t
pd
t
pd
t
pd
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
OH
V
OH
V
OL
V
OL
1.5 V 1.5 V
1.5 V 1.5 V
t
w
1.5 V 1.5 V
3.3 V
V
OL
V
OH
V
OH
–0.5 V
0 V
t
en
t
en
t
dis
t
dis
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V
R1
V
OL
+0.5 V
5 V
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
From Output
Under Test
Test
Point
Input
Out-of-Phase
Output
(see Note D)
Timing
Input
Data
Input
In-Phase
Output
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low–level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
NOTES: A. C
L
includes probe and jig capacitance and is 50 pF for t
pd
and t
en
, 5 pF for t
dis
.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For C suffix, use the voltage levels indicated in parentheses ( ). PRR 1 MHz,
t
r
= t
f
2 ns, duty cycle = 50%. For M suffix, use the voltage levels indicated in brackets [ ]. PRR 10 MHz, t
r
and t
f
2 ns,
duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 4. Load Circuit and Voltage Waveforms
B0892
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