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TIBPAL22V10ACNT

Part # TIBPAL22V10ACNT
Description 25NS TPD AT 180MA ICC - Rail/Tube
Category IC
Availability Out of Stock
Qty 0
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1 + $2.24000



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

ns
Pulse durationt
w
ns
t
su
Setup time before clock
TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
10
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) –5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN NOM MAX UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 5.5 V
V
IL
Low-level input voltage 0.8 V
I
OH
High-level output current –2 mA
I
OL
Low-level output current 12 mA
f
clock
Clock frequency
22 MHz
Clock high or low 20
Asynchronous reset high or low 30
Input 25
Feedback 25
Synchronous set 25
Asynchronous reset low (inactive) 30
t
h
Hold time, input, set, or feedback after clock 0 ns
T
A
Operating free-air temperature –55 125 °C
f
clock
(with feedback) =
1
t
su
t
pd
(CLK to Q)
, f
clock
(without feedback) =
1
t
w
(low) t
w
(high)
TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
11
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP
MAX UNIT
V
IK
V
CC
= 4.5 V, I
I
= –18 mA 1.2 V
V
OH
V
CC
= 4.5 V, I
OH
= –2 mA 2.4 3.5 V
V
OL
V
CC
= 4.5 V, I
OL
= 12 mA 0.25 0.5 V
I
OZH
V
CC
= 5.5 V, V
O
= 2.7 V 0.1 mA
I
OZL
V
CC
= 5.5 V, V
O
= 0.4 V 100 µA
I
I
V
CC
= 5.5 V, V
I
= 5.5 V 1 mA
I
IH
V
CC
= 5.5 V, V
I
= 2.7 V 25 µA
I
IL
V
CC
= 5.5 V, V
I
= 0.4 V 0.25 mA
I
OS
V
CC
= 5.5 V, V
O
= 0.5 V –30 –90 mA
I
CC
V
CC
= 5.5 V, V
I
= GND, Outputs open 120 180 mA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS MIN TYP
MAX UNIT
f
max
With feedback 22 MHz
t
pd
I, I/O I/O R1 = 390 , 15 30 ns
t
pd
I, I/O (reset) Q R2 = 750 , 15 35 ns
t
pd
CLK Q See Figure 4 10 20 ns
t
en
I, I/O I/O, Q 15 30 ns
t
dis
I, I/O I/O, Q 15 30 ns
All typical values are at V
CC
= 5 V, T
A
= 25°C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V
O
is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
f
max
(with feedback) =
1
t
su
t
pd
(CLK to Q)
, f
max
(without feedback) =
1
t
w
(low) t
w
(high)
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACT PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
12
preload procedure for registered outputs (see Notes 2 and 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below:
Step 1. With V
CC
at 5 V and pin 1 at V
IL
, raise pin 13 to V
IHH
.
Step 2. Apply either V
IL
or V
IH
to the output corresponding to the register to be preloaded.
Step 3. Pulse pin 1, clocking in preload data.
Step 4. Remove output voltage, then lower pin 13 to V
IL
. Preload can be verified by observing the voltage level
at the output pin.
t
d
t
su
t
w
t
d
V
IHH
V
IL
V
IL
V
OL
V
OH
V
IH
Pin 13
Pin 1
Registered I/O Input Output
V
IH
V
IL
Figure 2. Preload Waveforms
NOTES: 2. Pin numbers shown are for JT and NT packages only. If chip-carrier socket adapter is not used, pin numbers must be changed
accordingly.
3. t
d
=
t
su
=
t
w
= 100 ns to 1000 ns. V
IHH
= 10.25 V to 10.75 V.
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