Intel

Advanced+ Boot Block Flash Memory (C3)

Datasheet 61

C.5 Device Geometry Definition

Table 30. Device Geometry Definition

0x1E 1

[programming] supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

1E: --C6 12.6 V

0x1F 1 “n” such that typical single word program time-out =2

µs 1F: --05 32 µs

0x20 1 “n” such that typical max. buffer write time-out = 2

µs 20: --00 NA

0x21 1 “n” such that typical block erase time-out = 2

ms 21: --0A 1 s

0x22 1 “n” such that typical full chip erase time-out = 2

ms 22: --00 NA

0x23 1 “n” such that maximum word program time-out = 2

times typical 23: --04 512µs

0x24 1 “n” such that maximum buffer write time-out = 2

times typical 24: --00 NA

0x25 1 “n” such that maximum block erase time-out = 2

times typical 25: --03 8s

0x26 1 “n” such that maximum chip erase time-out = 2

times typical 26: --00 NA

Offset Length Description Add.

Hex

Code

Value

0x27 1 “n” such that device size = 2

in number of bytes 27 See Ta bl e 31

0x28 2 Flash device interface:

x8 async

28:00,29:00

x16 async

28:01,29:00

x8/x16 async

28:02,29:00

28:

29:

--01

--00

x16

0x2A 2 “n” such that maximum number of bytes in write buffer = 2

2A:

2B:

--00

0x2C 1

Number of erase block regions within device:

1. x = 0 means no erase blocking; the device erases in “bulk”

2. x specifies the number of device or partition regions

with one or more contiguous same-size erase blocks.

3. Symmetrically blocked partitions have one blocking region

4. Partition size = (total blocks) x (individual block size)

2C: --02 2

0x2D 4

Erase Block Region 1 Information

bits 0–15 = y, y+1 = number of identical-size erase blocks

bits 16–31 = z, region erase block(s) size are z x 256 bytes

2D:

2E:

2F:

30:

See Ta bl e 31

0x2D 14

Erase Block Region 2 Information

bits 0–15 = y, y+1 = number of identical-size erase blocks

bits 16–31 = z, region erase block(s) size are z x 256 bytes

31:

32:

33:

34:

See Ta bl e 31

Offset Length Description Add. Hex Code Value

Intel

Advanced+ Boot Block Flash Memory (C3)

62 Datasheet

C.6 Intel-Specific Extended Query Table

Certain flash features and commands are optional. The Intel-Specific Extended Query table

specifies this and other similar types of information.

Table 31. Device Geometry Details

Address

16 Mbit 32 Mbit 64 Mbit

-B -T -B -T -B -T

0x27 --15 -15 --16 -16 --17 --17

0x28 --01 --01 --01 --01 --01 --01

0x29 --00 --00 --00 -00 -00 -00

0x2A --00 --00 --00 -00 -00 -00

0x2B --00 --00 --00 -00 -00 -00

0x2C --02 --02 --02 --02 --02 --02

0x2D --07 --1E --07 --3E --07 --7E

0x2E --00 --00 --00 -00 -00 -00

0x2F --20 --00 --20 -00 --20 --00

0x30 --00 --01 --00 --01 --00 --01

0x31 --1E --07 --3E --07 --7E --07

0x32 --00 --00 --00 -00 -00 -00

0x33 --00 --20 --00 --20 --00 --20

0x34 --01 --00 --01 --00 --01 --00

Table 32. Primary-Vendor Specific Extended Query (Sheet 1 of 2)

Offset

P = 0x15

Length

Description

(Optional Flash Features and Commands)

Address Hex Code Value

0x(P+0)

0x(P+1)

0x(P+2)

Primary extended query table

Unique ASCII string “PRI”

35:

36:

37:

--50

--52

--49

“P”

“R”

“I”

0x(P+3) 1 Major version number, ASCII 38: --31 “1”

0x(P+4) 1 Minor version number, ASCII 39: --30 “0”

0x(P+5)

0x(P+6)

0x(P+7)

0x(P+8)

Optional feature and command support (1=yes,

0=no)

bits 9–31 are reserved; undefined bits are “0.” If bit

31 is “1” then another 31 bit field of optional

features follows at the end of the bit-30 field.

3A:

3B:

3C:

3D:

--66

--00

bit 0 Chip erase supported

bit 1 Suspend erase supported

bit 2 Suspend program supported

bit 3 Legacy lock/unlock supported

bit 4 Queued erase supported

bit 5 Instant individual block locking supported

bit 6 Protection bits supported

bit 7 Page mode read supported

bit 8 Synchronous read supported

bit 0 = 0

bit 1 = 1

bit 2 = 1

bit 3 = 0

bit 4 = 0

bit 5 = 1

bit 6 = 1

bit 7 = 0

bit 8 = 0

Yes

Intel

Advanced+ Boot Block Flash Memory (C3)

Datasheet 63

0x(P+9) 1

Supported functions after suspend: Read Array,

Status, Query

Other supported operations are:

bits 1–7 reserved; undefined bits are “0”

3E: --01

bit 0 Program supported after erase suspend bit 0 = 1 Yes

0x(P+A)

0x(P+B)

Block status register mask

bits 2–15 are Reserved; undefined bits are “0”

bit 0 Block Lock-Bit Status Register active

bit 1 Block Lock-Down Bit Status active

3F: --03

40: --00

bit 0 = 1 Yes

bit 1 = 1 Yes

0x(P+C) 1

logic supply highest performance program/

erase voltage

bits 0–3 BCD value in 100 mV

bits 4–7 BCD value in volts

41: --33 3.3 V

0x(P+D) 1

optimum program/erase supply voltage

bits 0–3 BCD value in 100 mV

bits 4–7 HEX value in volts

42: --C0 12.0 V

NOTES:

1. The variable P is a pointer which is defined at CFI offset 0x15.

Table 32. Primary-Vendor Specific Extended Query (Sheet 2 of 2)

Offset

P = 0x15

Length

Description

(Optional Flash Features and Commands)

Address Hex Code Value

Table 33. Protection Register Information

Offset

P = 0x35

Length

Description

(Optional Flash Features and Commands)

Address

Hex

Code

Value

0x(P+E) 1

Number of Protection register fields in JEDEC ID space.

“00h,” indicates that 256 protection bytes are available

43: --01 01

0x(P+F)

0x(P+10)

(0xP+11)

44:

45:

46:

--80

--00

--03

80h

00h

8byte

Protection Field 1: Protection Description

0x(P+12)

This field describes user-available One Time Programmable (OTP)

Protection register bytes. Some are pre-programmed with device-

unique serial numbers. Others are user programmable. Bits 0–15

point to the Protection register Lock byte, the section’s first byte.

The following bytes are factory pre-programmed and user-

programmable.

bits 0–7 = Lock/bytes JEDEC-plane physical low address

bits 8–15 = Lock/bytes JEDEC -plane physical high address

bits 16–23 = “n” such that 2

= factory pre-programmed bytes

bits 24–31 = “n” such that 2

= user programmable bytes

47: --03 8 byte

0x(P+13) Reserved for future use 48:

NOTES:

1. The variable P is a pointer which is defined at CFI offset 0x15.

Part #	TE28F800C3BA90
Description	NOR, Flash 512K x 16 48PinTSSOP
Category	IC
Availability	In Stock
Qty	375

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TE28F800C3BA90

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