Freelance Electronics Components Distributor
Closed Dec 25th-26th
800-300-1968
We Stock Hard to Find Parts

TE28F800C3BA90

Part # TE28F800C3BA90
Description NOR, Flash 512K x 16 48PinTSSOP
Category IC
Availability In Stock
Qty 375
Qty Price
1 - 78 $0.87249
79 - 157 $0.69403
158 - 236 $0.65437
237 - 315 $0.60810
316 + $0.54200
Manufacturer Available Qty
INTEL
Date Code: 0015
  • Shipping Freelance Stock: 190
    Ships Immediately
INTEL
Date Code: 0309
  • Shipping Freelance Stock: 16
    Ships Immediately
INTEL
Date Code: 0013
  • Shipping Freelance Stock: 167
    Ships Immediately
INTEL
Date Code: 0312
  • Shipping Freelance Stock: 2
    Ships Immediately



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Intel
£
Advanced+ Boot Block Flash Memory (C3)
Datasheet 37
I
PPR
V
PP
Read Current 1,4
2
±15 2 ±15 2 ±15 µA V
PP
V
CC
50 200 50 200 50 200 µA V
PP
>V
CC
I
PPW
V
PP
Program Current 1,4
0.05 0.1 0.05 0.1 0.05 0.1 mA
V
PP
=V
PP1,
Program in
Progress
822 8 22 8 22mA
V
PP
=V
PP2
(12v)
Program in
Progress
I
PPE
V
PP
Erase Current 1,4
0.05 0.1 0.05 0.1 0.05 0.1 mA
V
PP
=V
PP1,
Erase in
Progress
82216 451645mA
V
PP
=V
PP2
(12v) ,
Erase in
Progress
I
PPES
/
I
PPWS
V
CC
Erase Suspend
Current
1,4
0.2 5 0.2 5 0.2 5 µA
V
PP
=V
PP1,
Program or
Erase
Suspend in
Progress
50 200 50 200 50 200 µA
V
PP
=V
PP2
(12v) ,
Program or
Erase
Suspend in
Progress
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal V
CC
,T
A
=+2C.
2. The test conditions V
CC
Max, V
CCQ
Max, V
CC
Min, and V
CCQ
Min refer to the maximum or minimum V
CC
or
V
CCQ
voltage listed at the top of each column. V
CC
Max = 3.3 V for 0.25µm 32-Mbit devices.
3. Automatic Power Savings (APS) reduces I
CCR
to approximately standby levels in static operation (CMOS
inputs).
4. Sampled, not 100% tested.
5. I
CCES
or I
CCWS
is specified with device de-selected. If device is read while in erase suspend, current draw
is sum of I
CCES
and I
CCR
. If the device is read while in program suspend, current draw is the sum of I
CCWS
and I
CCR
.
Table 11. DC Current Characteristics (Sheet 3 of 3)
Sym Parameter
V
CC
2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V
Unit
Test
Conditions
V
CCQ
2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V
Note Typ Max Typ Max Typ Max
Intel
£
Advanced+ Boot Block Flash Memory (C3)
38 Datasheet
7.4 DC Voltage Characteristics
Table 12. DC Voltage Characteristics
Sym Parameter
V
CC
2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V
Unit Test ConditionsV
CCQ
2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V
Note Min Max Min Max Min Max
V
IL
Input Low
Voltage
–0.4
V
CC
*
0.22 V
–0.4 0.4 –0.4 0.4 V
V
IH
Input High
Voltage
2.0
V
CCQ
+0.3V
V
CCQ
0.4V
V
CCQ
+0.3V
V
CCQ
0.4V
V
CCQ
+0.3V
V
V
OL
Output Low
Voltage
–0.1 0.1 -0.1 0.1 -0.1 0.1 V
V
CC
=V
CC
Min
V
CCQ
=V
CCQ
Min
I
OL
=100µA
V
OH
Output High
Voltage
V
CCQ
–0.1V
V
CCQ
0.1V
V
CCQ
0.1V
V
V
CC
=V
CC
Min
V
CCQ
=V
CCQ
Min
I
OH
= –100 µA
V
PPLK
V
PP
Lock-
Out Voltage
11.0 1.0 1.0V
Complete Write
Protection
V
PP1
V
PP
during
Program /
Erase
Operations
1 1.65 3.6 1.65 3.6 1.65 3.6 V
V
PP2
1,2 11.4 12.6 11.4 12.6 11.4 12.6 V
V
LKO
V
CC
Prog/
Erase
Lock
Voltage
1.5 1.5 1.5 V
V
LKO2
V
CCQ
Prog/
Erase
Lock
Voltage
1.2 1.2 1.2 V
NOTES:
1. Erase and Program are inhibited when V
PP
<V
PPLK
and not guaranteed outside the valid V
PP
ranges of V
PP1
and V
PP2
.
2. Applying V
PP
= 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and
2500 cycles on the parameter blocks. V
PP
may be connected to 12 V for a total of 80 hours maximum.
Intel
£
Advanced+ Boot Block Flash Memory (C3)
Datasheet 39
8.0 AC Characteristics
8.1 AC Read Characteristics
Table 13. Read Operations—8 Mbit Density
#Sym Parameter
Density 8 Mbit
Unit
Product 90 ns 110 ns
V
CC
3.0V–3.6V 2.7V–3.6V 3.0V–3.6V 2.7V–3.6V
Note Min Max Min Max Min Max Min Max
R1 t
AVAV
Read Cycle Time 3,4 80 90 100 110 ns
R2 t
AVQV
Address to Output Delay 3,4 80 90 100 110 ns
R3 t
ELQV
CE# to Output Delay 1,3,4 80 90 100 110 ns
R4 t
GLQV
OE# to Output Delay 1,3,4 30 30 30 30 ns
R5 t
PHQV
RP# to Output Delay 3,4 150 150 150 150 ns
R6 t
ELQX
CE# to Output in Low Z 2,3,4 0 0 0 0 ns
R7 t
GLQX
OE# to Output in Low Z 2,3,4 0 0 0 0 ns
R8 t
EHQZ
CE#toOutputinHighZ 2,3,4 20 20 20 20 ns
R9 t
GHQZ
OE#toOutputinHighZ 2,3,4 20 20 20 20 ns
R10 t
OH
Output Hold from
Address, CE#, or OE#
Change, Whichever
Occurs First
2,3,4 0 0 0 0 ns
NOTES:
1.OE#maybedelayeduptot
ELQV
t
GLQV
after the falling edge of CE# without impact on t
ELQV
.
2. Sampled, but not 100% tested.
3. See Figure 8, “Read Operation Waveform” on page 42.
4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 for timing measurements and maximum allowable input
slew rate.
PREVIOUS678910111213141516171819NEXT