3-110
TELCOM SEMICONDUCTOR, INC.
Handshake Mode
The handshake mode provides an interface to a wide
variety of external devices. The byte enables may be used
as byte identification flags or as load enables and external
latches may be clocked by the rising edge of CE/LOAD. A
handshake interface to Intel microprocessors using an 8255
PPI is shown in Figure 19. The handshake operation with
the 8255 is controlled by inverting its Input Buffer Full (IBF)
flag to drive the SEND input to the TC7109A, and using the
CE/LOAD to drive the 8255 strobe. The internal control
register of the PPI should be set in MODE 1 for the port
used. If the 8255 IBF flag is LOW and the TC7109A is in
handshake mode, the next word will be strobed into the
port. The strobe will cause IBF to go HIGH (SEND goes
LOW), which will keep the enabled byte outputs active. The
PPI will generate an interrupt which, when executed, will
result in the data being read. The IBF will be reset LOW
when the byte is read, causing the TC7109A to sequence
into the next byte. The MODE input to the TC7109A is
connected to the control line on the PPI.
The data from every conversion will be sequenced in
two bytes in the system, if this output is left HIGH, or tied
HIGH separately. (The data access must take less time
than a conversion.) The output sequence can be obtained
on demand if this output is made to go from LOW to HIGH
and the interrupt may be used to reset the MODE bit.
Conversions may be obtained on command under soft-
ware control by driving the RUN/HOLD input to the TC7109A
by a bit of the 8255. Another peripheral device may be
serviced by the unused port of the 8255. The 8155 may be
used in a similar manner. The MCS650X microprocessors
are shown in Figure 20 with MODE and RUN/HOLD tied
HIGH to save port outputs.
The handshake mode is particularly useful for directly
interfacing to industry-standard UARTs (such as Western
Digital TR1602), providing a means of serially transmitting
converted data with minimum component count.
A typical UART connection is shown in Figure 1. In this
circuit, any word received by the UART causes the UART
DR (Data Ready) output to go HIGH. The MODE input to
the TC7109A goes HIGH, triggering the TC7109A into
handshake mode. The high-order byte is output to the
UART and when the UART has transferred the data to the
Transmitter register, TBRE (SEND) goes HIGH again, LBEN
will go HIGH, driving the UART DRR (Data Ready Reset)
which will signal the end of the transfer of data from the
TC7109A to the UART.
An extension of the typical connection to several
TC7109A's with one UART is shown in Figure 21. In this
circuit, the word received by the UART (available at the
RBR outputs when DR is HIGH) is used to select which
converter will handshake with the UART. Up to eight
TC7109A's may interface with one UART, with no external
components. Up to 256 converters may be accessed on
one serial line with additional components.
TC7109A
MODE
SEND
ANALOG
IN
HBEN
+5V
CA2
MC6800
OR
MCS650X
CONTROL
BUS
ADDRESS
BUS
CE/LOAD CA1
DATA
BUS
MC6820
CRA - -100-01
LBEN
RUN/HOLD
PA0–PA7
Figure 20. TC7109A Handshake Interface to MCS-6800, MCS650X Microprocessors
TC7109
TC7109A
12-BIT
µP-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
