7.19DRC1ControlRegisters,Channels1–7(0x96)

TAS5518C

8-ChannelDigitalAudioPWMProcessor

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SLES238A–SEPTEMBER2008–REVISEDJULY2009

BitsD31–D14aredon'tcare.Notethattheremustbea10-msdelaybetweenawritetoregister0x96and

awritetoregister0x97.

Table7-20.Channel1–7DCR1ControlRegisterFormat

D31D30D29D28D27D26D25D24FUNCTION

Unusedbits

D23D22D21D20D19D18D17D16FUNCTION

Unusedbits

D15D14D13D12D11D10D9D8FUNCTION

00––––Channel7(nodej):NoDRC

01––––Channel7(nodej):Pre-volumeDRC

10––––Channel7(nodej):Post-volumeDRC

11––––Channel7(nodej):NoDRC

––00––Channel6(nodeI):NoDRC

––01––Channel6(nodeI):Pre-volumeDRC

––10––Channel6(nodeI):Post-volumeDRC

––11––Channel6(nodei):NoDRC

––––00Channel5(nodem):NoDRC

––––01Channel5(nodem):Pre-volumeDRC

––––10Channel5(nodem):Post-volumeDRC

––––11Channel5(nodem):NoDRC

D7D6D5D4D3D2D1D0FUNCTION

00––––––Channel4(noden):NoDRC

01––––––Channel4(noden):Pre-volumeDRC

10––––––Channel4(noden):Post-volumeDRC

11––––––Channel4(noden):NoDRC

––00––––Channel3(nodeo):NoDRC

––01––––Channel3(nodeo):Pre-volumeDRC

––10––––Channel3(nodeo):Post-volumeDRC

––11––––Channel3(nodeo):NoDRC

––––00––Channel2(nodep):NoDRC

––––01––Channel2(nodep):Pre-volumeDRC

––––10––Channel2(nodep):Post-volumeDRC

––––11––Channel2(nodep):NoDRC

––––––00Channel1(nodeq):NoDRC

––––––01Channel1(nodeq):Pre-volumeDRC

––––––10Channel1(nodeq):Post-volumeDRC

––––––11Channel1(nodeq):NoDRC

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7.20DRC2ControlRegister,Channel8(0x97)

7.21DRC1DataRegisters(0x98–0x9C)

TAS5518C

8-ChannelDigitalAudioPWMProcessor

SLES238A–SEPTEMBER2008–REVISEDJULY2009

www.ti.com

Notethattheremustbea10-msdelaybetweenawritetoregister0x96andawritetoregister0x97.

Table7-21.Channel-8DRC2ControlRegisterFormat

D31–D2D1D0FUNCTION

0000Channel8(noder):noDRC

0001Channel8(noder):pre-volumeDRC

0010Channel8(noder):post-volumeDRC

0011Channel8(noder):noDRC

DRC1appliestochannels1,2,3,4,5,6,and7.

Table7-22.DRC1DataRegisterFormat

TOTAL

REGISTERNAMEDESCRIPTIONOFCONTENTSDEFAULTSTATE

SUB-

BYTES

ADDRESS

Channel1,2,3,4,5,6,and7DRC1u[31:28],E[27:24],E[23:16],E[15:8],E[7:0]0x00,0x00,0x88,0x3F

energy

0x988

Channel1,2,3,4,5,6,and7DRC1u[31:28],1–E[27:24],1–E[23:16],1–E[15:8],1–E[7:0]0x00,0x7F,0x77,0xC0

(1–energy)

Channel1,2,3,4,5,6,and7DRC1u[31:24],u[23:16],T1[15:8],T1[7:0]0x00,0x00,0x00,0x00

thresholdupper16bits(T1)

Channel1,2,3,4,5,6,and7DRC1T1[31:24],T1[23:16],T1[15:8],T1[7:0]0x0B,0x20,0xE2,0xB2

thresholdlower32bits(T1)

0x9916

Channel1,2,3,4,5,6,and7DRC1u[31:24],u[23:16],T2[15:8],T2[7:0]0x00,0x00,0x00,0x00

thresholdupper16bits(T2)

Channel1,2,3,4,5,6,and7DRC1T2[31:24],T2[23:16],T2[15:8],T2[7:0]0x06,0xF9,0xDE,0x58

thresholdlower32bits(T2)

Channel1,2,3,4,5,6,and7DRC1u[31:28],k0[27:24],k0[23:16],k0[15:8],k0[7:0]0x00,0x40,0x00,0x00

slope(k0)

Channel1,2,3,4,5,6,and7DRC1u[31:28],k1[27:24],k1[23:16],k1[15:8],k1[7:0]0x0F,0xC0,0x00,0x00

0x9A12

slope(k1)

Channel1,2,3,4,5,6,and7DRC1u[31:28],k2[27:24],k2[23:16],k2[15:8],k2[7:0]0x0F,0x90,0x00,0x00

slope(k2)

Channel1,2,3,4,5,6,and7DRC1u[31:24],u[23:16],O1[15:8],O1[7:0]0x00,0x00,0xFF,0xFF

offset-1upper16bits(O1)

Channel1,2,3,4,5,6,and7DRC1O1[31:24],O1[23:16],O1[15:8],O1[7:0]0xFF,0x82,0x30,0x98

offset-1lower32bits(O1)

0x9B16

Channel1,2,3,4,5,6,and7DRC1u[31:24],u[23:16],O2[15:8],O2[7:0]0x00,0x00,0x00,0x00

offset-2upper16bits(O2)

Channel1,2,3,4,5,6,and7DRC1O2[31:24],O2[23:16],O2[15:8],O2[7:0]0x01,0x95,0xB2,0xC0

offset-2lower32bits(O2)

Channel1,2,3,4,5,6,and7DRC1u[31:28],A[27:24],A[23:16],A[15:8],A[7:0]0x00,0x00,0x88,0x3F

attack

Channel1,2,3,4,5,6,and7DRC1u[31:28],1–A[27:24],1–A[23:16],1–A[15:8],1–A[7:0]0x00,0x7F,0x77,0xC0

(1–attack)

0x9C16

Channel1,2,3,4,5,6,and7DRC1u[31:28],D[27:24],D[23:16],D[15:8],D[7:0]0x00,0x00,0x00,0x56

decay

Channel1,2,3,4,5,6,and7DRC1u[31:28],1–D[27:24],1–D[23:16],1–D[15:8],1–D[7:0]0x00,0x3F,0xFF,0xA8

(1–decay)

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7.22DRC2DataRegisters(0x9D–0xA1)

7.23DRCBypassRegisters(0xA2–0xA9)

7.248×2OutputMixerRegisters(0xAA–0xAF)

TAS5518C

8-ChannelDigitalAudioPWMProcessor

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SLES238A–SEPTEMBER2008–REVISEDJULY2009

DRC2appliestochannel8.

Table7-23.DRC2DataRegisterFormat

TOTAL

REGISTERNAMEDESCRIPTIONOFCONTENTSDEFAULTSTATE

BYTES

SUBADDRESS

Channel8DRC2energyu[31:28],E[27:24],E[23:16],E[15:8],E[7:0]0x00,0x00,0x88,0x3F

0x9D8

Channel8DRC2(1–energy)u[31:28],1–E[27:24],1–E[23:16],1–E[15:8],1–E[7:0]0x00,0x7F,0x77,0xC0

Channel8DRC2thresholdu[31:24],u[23:16],T1[15:8],T1[7:0]0x00,0x00,0x00,0x00

upper16bits(T1)

Channel8DRC2thresholdT1[31:24],T1[23:16],T1[15:8],T1[7:0]0x0B,0x20,0xE2,0xB2

lower32bits(T1)

0x9E16

Channel8DRC2thresholdu[31:24],u[23:16],T2[15:8],T2[7:0]0x00,0x00,0x00,0x00

upper16bits(T2)

Channel8DRC2thresholdT2[31:24],T2[23:16],T2[15:8],T2[7:0]0x06,0xF9,0xDE,0x58

lower32bits(T2)

Channel8DRC2slope(k0)u[31:28],k0[27:24],k0[23:16],k0[15:8],k0[7:0]0x00,0x40,0x00,0x00

0x9F12Channel8DRC2slope(k1)u[31:28],k1[27:24],k1[23:16],k1[15:8],k1[7:0]0x0F,0xC0,0x00,0x00

Channel8DRC2slope(k2)u[31:28],k2[27:24],k2[23:16],k2[15:8],k2[7:0]0x0F,0x90,0x00,0x00

Channel8DRC2offset1upperu[31:24],u[23:16],O1[15:8],O1[7:0]0x00,0x00,0xFF,0xFF

16bits(O1)

Channel8DRC2offset1lowerO1[31:24],O1[23:16],O1[15:8],O1[7:0]0xFF,0x82,0x30,0x98

32bits(O1)

0xA016

Channel8DRC2offset2upperu[31:24],u[23:16],O2[15:8],O2[7:0]0x00,0x00,0x00,0x00

16bits(O2)

Channel8DRC2offset2lowerO2[31:24],O2[23:16],O2[15:8],O2[7:0]0x01,0x95,0xB2,0xC0

32bits(O2)

Channel8DRC2attacku[31:28],A[27:24],A[23:16],A[15:8],A[7:0]0x00,0x00,0x88,0x3F

Channel8DRC2(1–attack)u[31:28],1–A[27:24],1–A[23:16],1–A[15:8],1–A[7:0]0x00,0x7F,0x77,0xC0

0xA116

Channel8DRC2decayu[31:28],D[27:24],D[23:16],D[15:8],D[7:0]0x00,0x00,0x00,0x56

Channel8DRC2(1–decay)u[31:28],1–D[27:24],1–D[23:16],1–D[15:8],1–D[7:0]0x00,0x3F,0xFF,0xA8

DRCbypass/inlineforchannels1,2,3,4,5,6,7,and8aremappedintoregisters0xA2,0xA3,0xA4,

0xA5,0xA6,0xA7,0xA8,and0xA9,respectively.Eightbytesarewrittenforeachchannel.Eachgain

coefficientisin28-bit(5.23)format,so0x00800000isagainof1.Eachgaincoefficientiswrittenasa

32-bitwordwiththeupper4bitsnotused.

ToenableDRCforagivenchannel(withunitygain),bypass=0x00000000andinline=0x00800000.

TodisableDRCforagivenchannel,bypass=0x00800000andinline=0x00000000.

Table7-24.DRCBypassRegisterFormat

TOTAL

REGISTERNAMECONTENTSDEFAULTVALUE

BYTES

ChannelbassDRCbypassu[31:28],bypass[27:24],bypass[23:16],bypass[15:8],bypass[7:0]0x00,0x80,0x00,0x00

ChannelDRCinlineu[31:28],inline[27:24],inline[23:16],inline[15:8],inline[7:0]0x00,0x00,0x00,0x00

Thepass-throughoutputmixersettingis:

•DAPchannel1ismappedthoughthe8×2crossbarmixer(0xAA)toPWMchannel1

•DAPchannel2ismappedthoughthe8×2crossbarmixer(0xAB)toPWMchannel2

•DAPchannel3ismappedthoughthe8×2crossbarmixer(0xAC)toPWMchannel3

•DAPchannel4ismappedthoughthe8×2crossbarmixer(0xAD)toPWMchannel4

•DAPchannel5ismappedthoughthe8×2crossbarmixer(0xAE)toPWMchannel5

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Part #	TAS5518CPAG
Description	8 CHANNEL DIGITAL AUDIO PWM PROCESSOR
Category	IC
Availability	In Stock
Qty	2

TAS5518CPAG

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