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TAS5518CPAG

Part # TAS5518CPAG
Description 8 CHANNEL DIGITAL AUDIO PWM PROCESSOR
Category IC
Availability In Stock
Qty 2
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Texas Instruments
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

5.2Single-andMultiple-ByteTransfers
5.3Single-ByteWrite
A6 A5 A4 A3 A2 A1 A0
R/W
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress DataByte
T0036-01
TAS5518C
8-ChannelDigitalAudioPWMProcessor
SLES238A–SEPTEMBER2008–REVISEDJULY2009
www.ti.com
Theserial-controlinterfacesupportsbothsingle-byteandmultiple-byteread/writeoperationsforstatus
registersandthegeneralcontrolregistersassociatedwiththePWM.However,fortheDAPdata
processingregisters,theserial-controlinterfacesupportsonlymultiple-byte(four-byte)read/write
operations.
Duringmultiple-bytereadoperations,theTAS5518Crespondswithdata,abyteatatime,startingatthe
subaddressassigned,aslongasthemasterdevicecontinuestorespondwithacknowledges.Ifa
particularsubaddressdoesnotcontain32bits,theunusedbitsarereadaslogic0.
Duringmultiple-bytewriteoperations,theTAS5518Ccomparesthenumberofbytestransmittedtothe
numberofbytesthatarerequiredforeachspecificsubaddress.Ifawritecommandisreceivedfora
biquadsubaddress,theTAS5518Cexpectstoreceivefive32-bitwords.Iffewerthanfive32-bitdata
wordshavebeenreceivedwhenastopcommand(oranotherstartcommand)isreceived,thedata
receivedisdiscarded.Similarly,ifawritecommandisreceivedforamixercoefficient,theTAS5518C
expectstoreceiveone32-bitword.
SupplyingasubaddressforeachsubaddresstransactionisreferredtoasrandomI
2
Caddressing.The
TAS5518CalsosupportssequentialI
2
Caddressing.Forwritetransactions,ifasubaddressisissued
followedbydataforthatsubaddressandthe15subaddressesthatfollow,asequentialI
2
Cwrite
transactionhastakenplace,andthedataforall16subaddressesissuccessfullyreceivedbythe
TAS5518C.ForI
2
Csequentialwritetransactions,thesubaddressthenservesasthestartaddressandthe
amountofdatasubsequentlytransmitted,beforeastoporstartistransmitted,determineshowmany
subaddressesarewritten.Asistrueforrandomaddressing,sequentialaddressingrequiresthata
completesetofdatabetransmitted.Ifonlyapartialsetofdataiswrittentothelastsubaddress,thedata
forthelastsubaddressisdiscarded.However,allotherdatawrittenisaccepted;onlytheincompletedata
isdiscarded.
AsshowninFigure5-2,asingle-byte,data-writetransferbeginswiththemasterdevicetransmittingastart
conditionfollowedbytheI
2
Cdeviceaddressandtheread/writebit.Theread/writebitdeterminesthe
directionofthedatatransfer.Forawritedatatransfer,theread/writebitisa0.Afterreceivingthecorrect
I
2
Cdeviceaddressandtheread/writebit,theTAS5518Cdevicerespondswithanacknowledgebit.Next,
themastertransmitstheaddressbyteorbytescorrespondingtotheTAS5518Cinternalmemoryaddress
beingaccessed.Afterreceivingtheaddressbyte,theTAS5518Cagainrespondswithanacknowledgebit.
Next,themasterdevicetransmitsthedatabytetobewrittentothememoryaddressbeingaccessed.After
receivingthedatabyte,theTAS5518Cagainrespondswithanacknowledgebit.Finally,themaster
devicetransmitsastopconditiontocompletethesingle-byte,data-writetransfer.
Figure5-2.Single-ByteWriteTransfer
64SubmitDocumentationFeedback
I
2
CSerial-ControlInterface(SlaveAddresses0x36and0x37)
Not Recommended For New Designs
5.4Multiple-ByteWrite
D7 D0 ACK
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress LastDataByte
A6 A5 A1 A0 R/W ACK A7 A5 A1 A0 ACK D7 ACK
Start
Condition
Acknowledge Acknowledge Acknowledge
FirstDataByte
A4 A3A6
OtherDataBytes
ACK
Acknowledge
D0 D7 D0
T0036-02
5.5IncrementalMultiple-ByteWrite
TAS5518C
8-ChannelDigitalAudioPWMProcessor
www.ti.com
SLES238A–SEPTEMBER2008–REVISEDJULY2009
Amultiple-byte,data-writetransferisidenticaltoasingle-byte,data-writetransferexceptthatmultipledata
bytesaretransmittedbythemasterdevicetoTAS5518C,asshowninFigure5-3.Afterreceivingeach
databyte,theTAS5518Crespondswithanacknowledgebit.
Figure5-3.Multiple-ByteWriteTransfer
TheI
2
CsupportsaspecialmodewhichpermitsI
2
Cwriteoperationstobebrokenupintomultipledata
writeoperationsthataremultiplesoffourdatabytes.Theseare6-byte,10-byte,14-byte,18-byte,etc.,
writeoperationsthatarecomposedofadeviceaddress,read/writebit,subaddress,andanymultipleof
fourbytesofdata.Thispermitsthesystemtowritelargeregistervaluesincrementallywithoutblocking
otherI
2
Ctransactions.
ThisfeatureisenabledbytheappendsubaddressfunctionintheTAS5518C.Thisfunctionenablesthe
TAS5518CtoappendfourbytesofdatatoaregisterthatwasopenedbyapreviousI
2
Cregisterwrite
operationbuthasnotreceiveditscompletenumberofdatabytes.Becausethelengthofthelongregisters
isamultipleoffourbytes,usingfour-bytetransfershasonlyanintegralnumberofappendoperations.
Whenthecorrectnumberofbyteshasbeenreceived,theTAS5518Cstartsprocessingthedata.
Theproceduretoperformanincrementalmultibyte-writeoperationisasfollows:
1.StartanormalI
2
Cwriteoperationbysendingthedeviceaddress,writebit,registersubaddress,and
thefirstfourbytesofthedatatobewritten.Attheendofthatsequence,sendastopcondition.Atthis
point,theregisterhasbeenopenedandacceptstheremainingdatathatissentbywritingfour-byte
blocksofdatatotheappendsubaddress(0xFE).
2.Atalatertime,oneormoreappenddatatransfersareperformedtoincrementallytransferthe
remainingnumberofbytesinsequentialordertocompletetheregisterwriteoperation.Eachofthese
appendoperationsiscomposedofthedeviceaddress,writebit,appendsubaddress(0xFE),andfour
bytesofdatafollowedbyastopcondition.
3.Theoperationisterminatedduetoanerrorcondition,andthedataisflushed:
a.IfanewsubaddressiswrittentotheTAS5518Cbeforethecorrectnumberofbytesarewritten.
b.Ifmoreorfewerthanfourbytesaredatawrittenatthebeginningorduringanyoftheappend
operations.
c.Ifareadbitissent.
SubmitDocumentationFeedback65
I
2
CSerial-ControlInterface(SlaveAddresses0x36and0x37)
Not Recommended For New Designs
5.6Single-ByteRead
A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress DataByte
D7 D6 D1 D0 ACK
I CDevice Addressand
Read/WriteBit
2
Not
Acknowledge
R/WA1 A1
RepeatStart
Condition
T0036-03
5.7Multiple-ByteRead
A6 A0 ACK
Acknowledge
I CDevice Addressand
Read/WriteBit
2
R/WA6 A0 R/W ACK A0 ACK D7 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition
Not
Acknowledge
I CDevice Addressand
Read/WriteBit
2
Subaddress OtherDataBytes
A7 A6 A5 D7 D0 ACK
Acknowledge
D7 D0
T0036-04
TAS5518C
8-ChannelDigitalAudioPWMProcessor
SLES238A–SEPTEMBER2008–REVISEDJULY2009
www.ti.com
AsshowninFigure5-4,asingle-byte,data-readtransferbeginswiththemasterdevicetransmittingastart
conditionfollowedbytheI
2
Cdeviceaddressandtheread/writebit.Forthedata-readtransfer,bothawrite
andthenareadareactuallyperformed.Initially,awriteisperformedtotransfertheaddressbyteorbytes
oftheinternalmemoryaddresstoberead.Asaresult,theread/writebitisa0.Afterreceivingthe
TAS5518Caddressandtheread/writebit,theTAS5518Crespondswithanacknowledgebit.Inaddition,
aftersendingtheinternalmemoryaddressbyteorbytes,themasterdevicetransmitsanotherstart
conditionfollowedbytheTAS5518Caddressandtheread/writebitagain.Thistimetheread/writebitisa
1,indicatingareadtransfer.AfterreceivingtheTAS5518Caddressandtheread/writebit,theTAS5518C
againrespondswithanacknowledgebit.Next,theTAS5518Ctransmitsthedatabytefromthememory
addressbeingread.Afterreceivingthedatabyte,themasterdevicetransmitsanot-acknowledgefollowed
byastopconditiontocompletethesingle-byte,data-readtransfer.
Figure5-4.Single-ByteReadTransfer
Amultiple-byte,data-readtransferisidenticaltoasingle-byte,data-readtransferexceptthatmultipledata
bytesaretransmittedbytheTAS5518Ctothemasterdevice,asshowninFigure5-5.Exceptforthelast
databyte,themasterdevicerespondswithanacknowledgebitafterreceivingeachdatabyte.
Figure5-5.Multiple-ByteReadTransfer
66SubmitDocumentationFeedback
I
2
CSerial-ControlInterface(SlaveAddresses0x36and0x37)
Not Recommended For New Designs
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