BLOCK DIAGRAM
FEATURES
DESCRIPTION
Rev.: F Amendment: /0
Issue Date: October, 1998
The SY100S815 is a low skew 1-to-4 PECL differential
driver designed for clock distribution in new, high-
performance PECL systems. It accepts either a PECL
clock input or a TTL input by using the TTL enable pin TEN.
When the TTL enable pin is HIGH, the TTL input is enabled
and the PECL input is disabled. When the enable pin is set
LOW, the TTL input is disabled and the PECL input is
enabled.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the S815 shares a common set of “basic”
processing with the other members of the ECLinPS family,
wafer characterization at the point of device personalization
allows for tighter control of parameters, including
propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50Ω, even if only one side is being used. In
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same VCCO as the pair(s) being used on that side) in order
to maintain minimum skew.
■ Quad PECL version of popular ECLinPS E111
■ Low skew
■ Guaranteed skew spec
■ TTL enable input
■ Selectable TTL or PECL clock input
■ Single +5V supply
■ Differential internal design
■ PECL I/O fully compatible with industry standard
■ Internal 75k
Ω PECL input pull-down resistors
■ Available in 16-pin SOIC package
ClockWorks™
SY100S815
SINGLE SUPPLY QUAD
PECL/TTL-TO-PECL
Pin Function
EIN, EIN Differential PECL Input Pair
TIN TTL Input
TEN TTL Input Enable
Q0, Q0 – Q3, Q3 Differential PECL Outputs
VCC PECL VCC (+5.0V)
V
EE PECL Ground (0V)
PIN CONFIGURATION
PIN NAMES
1
2
3
4
5
6
7
8
15
16
14
13
12
11
10
9
VCC
TIN
Q3
Q2
Q2
VCCO
EIN
TEN
VEE
Q0
Q0
Q1
VCCO
TOP VIEW
SOIC
Z16-1
Q3
EIN
Q1
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
EIN
EIN
0
1
TIN
TEN
1
