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SST25VF010A-33-4I-SAE

Part # SST25VF010A-33-4I-SAE
Description 2.7V TO 3.6V 1MBIT SPI SERIALFLASH - Rail/Tube
Category IC
Availability Out of Stock
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

©2006 Silicon Storage Technology, Inc.
S71265-02-000 1/06
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Data Sheet
FEATURES:
Single 2.7-3.6V Read and Write Operations
Serial Interface Architecture
SPI Compatible: Mode 0 and Mode 3
33 MHz Max Clock Frequency
Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
Low Power Consumption:
Active Read Current: 7 mA (typical)
Standby Current: 8 µA (typical)
Flexible Erase Capability
Uniform 4 KByte sectors
Uniform 32 KByte overlay blocks
Fast Erase and Byte-Program:
Chip-Erase Time: 70 ms (typical)
Sector- or Block-Erase Time: 18 ms (typical)
Byte-Program Time: 14 µs (typical)
Auto Address Increment (AAI) Programming
Decrease total chip programming time over
Byte-Program operations
End-of-Write Detection
Software Status
Hold Pin (HOLD#)
Suspends a serial sequence to the memory
without deselecting the device
Write Protection (WP#)
Enables/Disables the Lock-Down function of the
status register
Software Write Protection
Write protection through Block-Protection bits in
status register
Temperature Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Extended: -20°C to +85°C
Packages Available
8-lead SOIC 150 mil body width
8-contact WSON (5mm x 6mm)
All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
SST’s serial flash family features a four-wire, SPI-compati-
ble interface that allows for a low pin-count package occu-
pying less board space and ultimately lowering total system
costs. SST25VF010A SPI serial flash memory is manufac-
tured with SST’s proprietary, high performance CMOS
SuperFlash Technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The SST25VF010A device significantly improves perfor-
mance, while lowering power consumption. The total
energy consumed is a function of the applied voltage, cur-
rent, and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to pro-
gram and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less than
alternative flash memory technologies. The SST25VF010A
device operates with a single 2.7-3.6V power supply.
The SST25VF010A device is offered in both 8-lead SOIC
and 8-contact WSON packages. See Figure 1 for the pin
assignments.
1 Mbit SPI Serial Flash
SST25VF010A
SST25VF010A1Mb Serial Peripheral Interface (SPI) flash memory
2
Data Sheet
1 Mbit SPI Serial Flash
SST25VF010A
©2006 Silicon Storage Technology, Inc. S71265-02-000 1/06
1265 B1.0
I/O Buffers
and
Data Latches
SuperFlash
Memory
X - Decoder
Control Logic
Address
Buffers
and
Latches
CE#
Y - Decoder
SCK SI SO WP# HOLD#
Serial Interface
FUNCTIONAL BLOCK DIAGRAM
Data Sheet
1 Mbit SPI Serial Flash
SST25VF010A
3
©2006 Silicon Storage Technology, Inc. S71265-02-000 1/06
PIN DESCRIPTION
FIGURE 1: PIN ASSIGNMENTS
TABLE 1: PIN DESCRIPTION
Symbol Pin Name Functions
SCK Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input, while output
data is shifted out on the falling edge of the clock input.
SI Serial Data
Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO Serial Data
Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of
any command sequence.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device.
V
DD
Power Supply To provide power supply (2.7-3.6V).
V
SS
Ground
T1.0 1265
1
2
3
4
8
7
6
5
CE#
SO
WP#
V
SS
V
DD
HOLD#
SCK
SI
Top View
1265 08-soic P1.0
8-LEAD SOIC 8-CONTACT WSON
1
2
3
4
8
7
6
5
CE#
SO
WP#
V
SS
Top View
V
DD
HOLD#
SCK
SI
1265 08-wson P2.0
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