Freelance Electronics Components Distributor
Closed Dec 25th-26th
800-300-1968
We Stock Hard to Find Parts

SRC4184IPAG

Part # SRC4184IPAG
Description 4-CH SAMPLE RATE CONVERTER (LOW PERF) - Trays
Category IC
Availability In Stock
Qty 17
Qty Price
1 - 3 $11.01157
4 - 7 $8.75921
8 - 10 $8.25868
11 - 14 $7.67473
15 + $6.84052
Manufacturer Available Qty
Burr-Brown Corporation
  • Shipping Freelance Stock: 10
    Ships Immediately
Texas Instruments
  • Shipping Freelance Stock: 7
    Ships Immediately



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

"#$%#
SBFS026B − JUNE 2004 − REVISED SEPTEMBER 2007
www.ti.com
4
ELECTRICAL CHARACTERISTICS (continued)
All specifications at T
A
= +25°C, VDD33 = +3.3V, V
IO
= +3.3V, REGEN = High, and VDD18 floating, unless otherwise noted.
SRC4184
PARAMETER UNITSMAXTYPMINCONDITIONS
SWITCHING CHARACTERISTICS (continued)
Output Serial Port Timing
SDOUT Data Delay Time t
DOPD
10 ns
SDOUT Data Hold Time t
DOH
2 ns
BCKO Pulsewidth High t
SOH
10 ns
BCKO Pulsewidth Low t
SOL
5 ns
TDM Mode Timing
LRCKO Setup Time t
LROS
10 ns
LRCKO Hold Time t
LROH
10 ns
TDMI Data Setup Time t
TDMS
10 ns
TDMI Data Hold Time t
TDMH
10 ns
SPI Timing
CCLK Frequency 25 MHz
CDATA Setup Time t
CDS
12 ns
CDATA Hold Time t
CDH
8 ns
CS Falling to CCLK Rising t
CSCR
15 ns
CCLK Falling to CS Rising t
CFCS
12 ns
CCLK Falling to CDOUT Data Valid t
CFDO
5 ns
CS Rising to CDOUT High Impedance t
CSZ
5 ns
POWER SUPPLIES
(4,
5)
Operating Voltage
VDD18 REGEN = 0 +1.65 +1.8 +2.0 V
VDD33 REGEN = 1 +3.0 +3.3 +3.6 V
V
IO
+1.65 +3.3 +3.6 V
Supply Current VDD18 = +1.8V, V
IO
= +1.8V, REGEN = 0
IDD, Hard Power-Down RST = 0, No Clocks 100 µA
IDD, Soft Power-Down PDN Bit = 0, No Clocks 100 µA
IDD, Dynamic f
sIN
= 96kHz, f
sOUT
= 192kHz 80 mA
IIO, Hard Power-Down RST = 0, No Clocks 100 µA
IIO, Soft Power-Down PDN Bit = 0, No Clocks 100 µA
IIO, Dynamic f
sIN
= 96kHz, f
sOUT
= 192kHz 6 mA
Total Power Dissipation VDD18 = +1.8V, V
IO
= +1.8V, REGEN = 0
P
D
, Hard Power-Down RST = 0, No Clocks 1 mW
P
D
, Soft Power-Down PDN Bit = 0, No Clocks 360 µW
P
D
, Dynamic f
sIN
= f
sOUT
= 192kHz 155 mW
Supply Current VDD33 = +3.3V, V
IO
= +3.3V, REGEN = 1
IDD, Hard Power-Down RST = 0, No Clocks 100 µA
IDD, Soft Power-Down PDN Bit = 0, No Clocks 6 mA
IDD, Dynamic f
sIN
= 96kHz, f
sOUT
= 192kHz 90 mA
IIO, Hard Power-Down RST = 0, No Clocks 100 µA
IIO, Soft Power-Down PDN Bit = 0, No Clocks 100 µA
IIO, Dynamic f
sIN
= 96kHz, f
sOUT
= 192kHz 6 mA
Total Power Dissipation VDD33 = +3.3V, V
IO
= +3.3V, REGEN = 1
P
D
, Hard Power-Down RST = 0, No Clocks 1 mW
P
D
, Soft Power-Down PDN Bit = 0, No Clocks 21 mW
P
D
, Dynamic f
sIN
= f
sOUT
= 192kHz 320 mW
(1)
Dynamic performance is measured with an Audio Precision System Two Cascade or Cascade Plus test system.
(2)
f
sMIN
= min (f
sIN
, f
sOUT
).
(3)
f
sMAX
= max (f
sIN
, f
sOUT
).
(4)
Power-supply current for power-down modes is measured without loading.
(5)
Dynamic current is measured with active loading and the excercized output pins equal to ±2mA.
"#$%#
SBFS026B − JUNE 2004 − REVISED SEPTEMBER 2007
www.ti.com
5
PIN CONFIGURATION
Top View TQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
IFMTB0
IFMTB1
IFMTB2
OFMTB0
OFMTB1
OWLB0
OWLB1
BYPB
LGRPB0
LGRPB1
DDNB
DEMB0
DEMB1 (CDOUT)
MODEB0 (CS)
MODEB1 (CCLK)
MODEB2 (CDIN)
SDOUTA
BCKOA
LRCKOA
TDMIA
BCKIA
LRCKIA
SDINA
DGND
V
IO
SDINB
LRCKIB
BCKIB
TDMIB
LRCKOB
BCKOB
SDOUTB
RATIOA
RDYA
MUTEA
RCKIA
RST
H/S
DGND
VDD33
VDD33
REGEN
VDD18
VDD18
RCKIB
MUTEB
RDYB
RATIOB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IFMTA0
IFMTA1
IFMTA2
OFMTA0
OFMTA1
OWLA0
OWLA1
BYPA
LGRPA0
LGRPA1
DDNA
DEMA0
DEMA1
MODEA0
MODEA1
MODEA2
64 63 62 61 60 59 58
57 56 55 54
17 18 19 20 21 22 23 24 25 26 27
53
28 29 30 31 32
52 51 50 49
SRC4184
"#$%#
SBFS026B − JUNE 2004 − REVISED SEPTEMBER 2007
www.ti.com
6
PIN DESCRIPTIONS
PIN # NAME I/O DESCRIPTION
1 IFMTA0 Input SRC A Audio Input Data Format
(1)
2 IFMTA1 Input SRC A Audio Input Data Format
(1)
3 IFMTA2 Input SRC A Audio Input Data Format
(1)
4 OFMTA0 Input SRC A Audio Output Data Format
(1)
5 OFMTA1 Input SRC A Audio Output Data Format
(1)
6 OWLA0 Input SRC A Audio Output Data Word Length
(1)
7 OWLA1 Input SRC A Audio Output Data Word Length
(1)
8 BYPA Input SRC A Bypass Mode (Active High)
9 LGRPA0 Input SRC A Low Group Delay Mode
(1)
10 LGRPA1 Input SRC A Low Group Delay Mode
(1)
11 DDNA Input SRC A Direct Downsampling Mode (Active High)
(1)
12 DEMA0 Input SRC A Digital De-Emphasis Filter Mode
(1)
13 DEMA1 Input SRC A Digital De-Emphasis Filter Mode
(1)
14 MODEA0 Input SRC A Serial Port Mode
(1)
15 MODEA1 Input SRC A Serial Port Mode
(1)
16 MODEA2 Input SRC A Serial Port Mode
(1)
17 RATIOA Output SRC A Ratio Flag
18 RDYA Output SRC A Ready Flag (Active Low)
19 MUTEA Input SRC A Output Soft Mute
20 RCKIA Input SRC A Reference Clock
21 RST Input Reset and Power-Down (Active Low)
22 H/S Input Control Mode (0 = Software, 1 = Hardware)
23 DGND Ground Digital Ground
24, 25 VDD33 Power Core Supply, +3.3V. Required when REGEN is high. When REGEN is low, VDD33 must be left unconnected.
26 REGEN Input Voltage Regulator Enable (Active High)
27, 28 VDD18 Power Core Supply, +1.8V. Required when REGEN is low. When REGEN is high, VDD18 must be left unconnected.
29 RCKIB Input SRC B Reference Clock
30 MUTEB Input SRC B Output Soft Mute
31 RDYB Output SRC B Ready Flag (Active Low)
32 RATIOB Output SRC B Ratio Flag
33 MODEB2 or CDIN Input SRC B Serial Port Mode
(1)
or SPI Port Serial Data Input
(2)
34 MODEB1 or CCLK Input SRC B Serial Port Mode
(1)
or SPI Port Data Clock
(2)
35 MODEB0 or CS Input SRC B Serial Port Mode
(1)
or SPI Port Chip Select (Active Low)
(2)
36 DEMB1 or CDOUT I/O SRC B Digital De-Emphasis Filter Mode
(1)
or SPI Port Serial Data Output
(2)
37 DEMB0 Input SRC B Digital De-Emphasis Filter Mode
(1)
38 DDNB Input SRC B Direct Downsampling Mode (Active High)
(1)
39 LGRPB1 Input SRC B Low Group Delay Mode
(1)
40 LGRPB0 Input SRC B Low Group Delay Mode
(1)
41 BYPB Input SRC B Bypass Mode (Active High)
42 OWLB1 Input SRC B Audio Output Data Word Length
(1)
43 OWLB0 Input SRC B Audio Output Data Word Length
(1)
44 OFMTB1 Input SRC B Audio Output Data Format
(1)
45 OFMTB0 Input SRC B Audio Output Data Format
(1)
46 IFMTB2 Input SRC B Audio Input Data Format
(1)
47 IFMTB1 Input SRC B Audio Input Data Format
(1)
48 IFMTB0 Input SRC B Audio Input Data Format
(1)
49 SDOUTB Output SRC B Audio Output Data
50 BCKOB I/O SRC B Audio Output Bit Clock
51 LRCKOB I/O SRC B Audio Output Left/Right or Word Clock
52 TDMIB Input SRC B TDM Input Data (TDM Format Only)
53 BCKIB I/O SRC B Audio Input Bit Clock
54 LRCKIB I/O SRC B Audio Input Left/Right or Word Clock
55 SDINB Input SRC B Audio Input Data
56 V
IO
Power Digital I/O Supply, +1.65V to +3.6V
57 DGND Ground Digital Ground
58 SDINA Input SRC A Audio Input Data
59 LRCKIA I/O SRC A Audio Input Left/Right or Word Clock
60 BCKIA I/O SRC A Audio Input Bit Clock
61 TDMIA Input SRC A TDM Input Data (TDM Format Only)
62 LRCKOA I/O SRC A Audio Output Left/Right or Word Clock
63 BCKOA I/O SRC A Audio Output Bit Clock
64 SDOUTA Output SRC A Audio Output Data
(1)
Disabled in Software control mode.
(2)
Disabled in Hardware control mode.
PREVIOUS12345678NEXT