MPC5200B Data Sheet, Rev. 1
System Design Information
Freescale Semiconductor70
5.1.2 Power Down Sequence
If VDD_CORE/PLL_AVDD are powered down first, then sense circuits in the I/O pads will cause all
output drivers to be in a high impedance state. There is no limit on how long after VDD_CORE and
PLL_AVDD power down before VDD_IO or VDD_IO_MEM must power down. VDD_CORE should not
lag VDD_IO, VDD_IO_MEM, or PLL_AVDD going low by more than 0.5V during power down or there
will be undesired high current in the ESD protection diodes. There are no requirements for the fall times
of the power supplies.
The recommended power down sequence is as follows:
Drop VDD_CORE/PLL_AVDD to 0V.
Drop VDD_IO/VDD_IO_MEM supplies.
5.2 System and CPU Core AVDD Power Supply Filtering
Each of the independent PLL power supplies require filtering external to the device. The following
drawing is a recommendation for the required filter circuit.
Figure 52. Power Supply Filtering
5.3 Pull-up/Pull-down Resistor Requirements
The MPC5200B requires external pull-up or pull-down resistors on certain pins.
5.3.1 Pull-down Resistor Requirements for TEST pins
The MPC5200B requires pull-down resistors on the test pins TEST_MODE_0, TEST_MODE_1,
TEST_SEL_1.
5.3.2 Pull-up Requirements for the PCI Control Lines
If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as
indicated by the PCI Local Bus specification [4]. This is also required for MOST/Graphics and Large Flash
Mode.
PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to
ensure that they contain stable values when no agent is actively driving the bus. This includes
AVDD device pinPower
Supply
source
< 1 Ω
10 Ω
200-400 pF
10 µF
