Electrical and Thermal Characteristics
MPC5200B Data Sheet, Rev. 1
Freescale Semiconductor 43
Figure 29. Ethernet Timing Diagram—MII Async
Figure 30. Ethernet Timing Diagram—MII Serial Management
Table 34. MII Serial Management Channel Signal Timing
Sym Description Min Max Unit SpecID
t
10
MDC falling edge to MDIO output delay 0 25 ns A9.10
t
11
MDIO (input) to MDC rising edge setup 10 — ns A9.11
t
12
MDIO (input) to MDC rising edge hold 10 — ns A9.12
t
13
MDC pulse width high
(1)
NOTES:
1
MDC is generated by MPC5200B with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED
control register is changed during operation. See the MPC5200B User Manual [1].
160 — ns A9.13
t
14
MDC pulse width low
(1)
160 — ns A9.14
t
15
MDC period
(2)
2
The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII
characteristic) by programming the FEC MII_SPEED control register. See the MPC5200B User Manual [1].
400 — ns A9.15
t
9
CRS, COL
t
14
t
13
t
12
MDC (Output)
MDIO (Input)
MDIO (Output)
t
11
t
10
t
15
