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INA333AIDGKR

Part # INA333AIDGKR
Description SP Amp INSTR Amp Single R-R O/P ±2.75V/5.5V 8-Pin VSSOP T/
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

80
70
60
50
40
30
20
10
0
0
1.0
V (V)
CM
I ( A)m
Q
5.0
2.0
V =5V
S
3.0 4.0
V =1.8V
S
INA333
SBOS445 JULY 2008 ......................................................................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At T
A
= +25 ° C, R
L
= 10k , V
REF
= 0, and G = 1, unless otherwise noted.
QUIESCENT CURRENT vs COMMON-MODE VOLTAGE
Figure 31.
10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): INA333
APPLICATION INFORMATION
SETTING THE GAIN
A
1
A
2
A
3
6
150kW150kW
150kW150kW
7
4
3
8
1
2
V
IN-
V
IN+
R
G
V+
V-
INA333
G=1+
100kW
R
G
5
RFIFilter
50kW
50kW
RFIFilter
Load
V =G (V´ V- )
O IN+ IN-
0.1 Fm
0.1 Fm
+
-
V
O
R
G
Alsodrawninsimplifiedform:
INA333
Ref
V
O
V
IN-
V
IN+
Ref
RFIFilter
RFIFilter
INA333
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...................................................................................................................................................................................................... SBOS445 JULY 2008
Figure 32 shows the basic connections required for Table 1 lists several commonly-used gains and
operation of the INA333. Good layout practice resistor values. The 100k term in Equation 1 comes
mandates the use of bypass capacitors placed close from the sum of the two internal feedback resistors of
to the device pins as shown. A
1
and A
2
. These on-chip resistors are laser trimmed
to accurate absolute values. The accuracy and
The output of the INA333 is referred to the output
temperature coefficient of these resistors are included
reference (REF) terminal, which is normally
in the gain accuracy and drift specifications of the
grounded. This connection must be low-impedance to
INA333.
assure good common-mode rejection. Although 15
or less of stray resistance can be tolerated while The stability and temperature drift of the external gain
maintaining specified CMRR, small stray resistances setting resistor, R
G
, also affects gain. The contribution
of tens of ohms in series with the REF pin can cause of R
G
to gain accuracy and drift can be directly
noticeable degradation in CMRR. inferred from the gain Equation 1 . Low resistor values
required for high gain can make wiring resistance
important. Sockets add to the wiring resistance and
contribute additional gain error (possibly an unstable
Gain of the INA333 is set by a single external
gain error) in gains of approximately 100 or greater.
resistor, R
G
, connected between pins 1 and 8. The
To ensure stability, avoid parasitic capacitance of
value of R
G
is selected according to Equation 1 :
more than a few picofarads at the R
G
connections.
Careful matching of any parasitics on both R
G
pins
G = 1 + (100k /R
G
) (1)
maintains optimal CMRR over frequency.
Figure 32. Basic Connections
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): INA333
INTERNAL OFFSET CORRECTION
NOISE PERFORMANCE
OFFSET TRIMMING
INPUT BIAS CURRENT RETURN PATH
10kW
OPA333
±10mV
AdjustmentRange
100W
100W
100 Am
1/2REF200
100 Am
1/2REF200
V+
V-
R
G
INA333
Ref
V
O
V
IN-
V
IN+
INA333
SBOS445 JULY 2008 ......................................................................................................................................................................................................
www.ti.com
Table 1. Commonly-Used Gains and Resistor Values
DESIRED GAIN R
G
( ) NEAREST 1% R
G
( )
1 NC
(1)
NC
2 100k 100k
5 25k 24.9k
10 11.1k 11k
20 5.26k 5.23k
50 2.04k 2.05
100 1.01k 1k
200 502.5 499
500 200.4 200
1000 100.1 100
(1) NC denotes no connection. When using the SPICE model, the simulation will not converge unless a resistor is connected to the R
G
pins;
use a very large resistor value.
The INA333 internal op amps use an auto-calibration
technique with a time-continuous 350kHz op amp in
the signal path. The amplifier is zero-corrected every
The auto-calibration technique used by the INA333
8 µ s using a proprietary technique. Upon power-up,
results in reduced low frequency noise, typically only
the amplifier requires approximately 100 µ s to achieve
50nV/ Hz, (G = 100). The spectral noise density can
specified V
OS
accuracy. This design has no aliasing
be seen in detail in Figure 8 . Low frequency noise of
or flicker noise.
the INA333 is approximately 1 µ V
PP
measured from
0.1Hz to 10Hz, (G = 100).
Most applications require no external offset
adjustment; however, if necessary, adjustments can
The input impedance of the INA333 is extremely
be made by applying a voltage to the REF terminal.
high approximately 100G . However, a path must
Figure 33 shows an optional circuit for trimming the
be provided for the input bias current of both inputs.
output offset voltage. The voltage applied to REF
This input bias current is typically ± 70pA. High input
terminal is summed at the output. The op amp buffer
impedance means that this input bias current
provides low impedance at the REF terminal to
changes very little with varying input voltage.
preserve good common-mode rejection.
Input circuitry must provide a path for this input bias
current for proper operation. Figure 34 illustrates
various provisions for an input bias current path.
Without a bias current path, the inputs will float to a
potential that exceeds the common-mode range of
the INA333, and the input amplifiers will saturate. If
the differential source resistance is low, the bias
current return path can be connected to one input
(see the thermocouple example in Figure 34 ). With
higher source impedance, using two equal resistors
provides a balanced input with possible advantages
of lower input offset voltage as a result of bias current
and better high-frequency common-mode rejection.
Figure 33. Optional Trimming of Output Offset
Voltage
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Product Folder Link(s): INA333
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