SLLS318C − NOVEMBER 1998 − REVISED JULY 2006
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D 3:21 Data Channel Expansion at up to
178.5 Mbytes/s Throughput
D Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
D Three Data Channels and Clock
Low-Voltage Differential Channels In and
21 Data and Clock Low-Voltage TTL
Channels Out
D Operates From a Single 3.3-V Supply
D Tolerates 4-kV HBM ESD
D Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal
Pitch
D Consumes Less Than 1 mW When Disabled
D Wide Phase-Lock Input Frequency Range
31 MHz to 68 MHz
D No External Components Required for PLL
D Inputs Meet or Exceed the Standard
Requirements of ANSI EIA/TIA-644
Standard
D Improved Replacement for the DS90C364
and SN75LVDS86
D Improved Jitter Tolerance
D Available in Q-Temp Automotive
High Reliability Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
description
The SN65LVDS86AQ/SN75LVDS86A FlatLink receiver contains three serial-in 7-bit parallel-out shift registers
and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions
allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84, or ’85, over
four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data
at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input
clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. The
’LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).
The ’LVDS86A requires only four line-termination resistors for the differential inputs and little or no control. The
data bus appears the same at the input to the transmitter and output of the receiver with the data transmission
transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN
)
active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level
on this signal clears all internal registers to a low level.
Copyright 2006, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments Incorporated.
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48
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31
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29
28
27
26
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D17
D18
GND
D19
D20
NC
LVDSGND
A0M
A0P
A1M
A1P
LVDSV
CC
LVDSGND
A2M
A2P
CLKINM
CLKINP
LVDSGND
PLLGND
PLLV
CC
PLLGND
SHTDN
CLKOUT
D0
V
CC
D16
D15
D14
GND
D13
V
CC
D12
D11
D10
GND
D9
V
CC
D8
D7
D6
GND
D5
D4
D3
V
CC
D2
D1
GND
DGG PACKAGE
(TOP VIEW)
NC − Not connected
