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SN74VMEH22501ADGGR

Part # SN74VMEH22501ADGGR
Description Bus XCVR Single 10-CH 3-ST 48-Pin TSSOP T/R - Tape and Ree
Category IC
Availability Out of Stock
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1 + $2.69950

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.


        
        
SCES620 – DECEMBER 2004
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
B PORT
V
OH
V
OL
t
h
t
su
From Output
Under Test
C
L
= 50 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500 Ω
500 Ω
t
PLH
t
PHL
Output Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
3 V
0 V
V
OH
V
OL
0 V
V
OL
+ 0.3 V
V
OH
− 0.3 V
≈0 V
3 V
0 V
0 V
t
w
Input
3 V
3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Timing
Input
Data
Input
Output
Input
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
A-to-B Skew
Open
6 V
GND
Open
TEST S1
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, Z
O
= 50 Ω, t
r
≈ 2 ns, t
f
≈ 2ns
.
D. The outputs are measured one at a time, with one transition per measurement.
6 V
0 V
3 V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
Figure 2. Load Circuit and Voltage Waveforms

        
        
SCES620 – DECEMBER 2004
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics tables show the switching characteristics of the device into the lumped load
shown in the parameter measurement information (PMI) (see Figures 1 and 2). All logic devices currently are tested
into this type of load. However, the designer’s backplane application probably is a distributed load. For this reason,
this device has been designed for optimum performance in the VME64x backplane as shown in Figure 3.
5 V
0.42” 0.84”
1.5” 1.5”
1.5”1.5”
0.84” 0.42”
Rcvr
Rcvr
Rcvr
Slot 2 Slot 3 Slot 19 Slot 20
Conn.
Conn. Conn. Conn.
1.5”
Rcvr
Slot 1
Conn.
0.42”
Drvr
1.5”
Slot 21
Conn.
0.42”
330 Ω
470 Ω
Z
O
†
5 V
330 Ω
470 Ω
Z
O
‡
†
Unloaded backplane trace natural impedence (Z
O
) is 45 Ω. 45 Ω to 60 Ω is allowed, with 50 Ω being ideal.
‡
Card stub natural impedence (Z
O
) is 60 Ω.
Rcvr
Figure 3. VME64x Backplane
The following switching characteristics tables derived from TI-SPICE models show the switching characteristics of
the device into the backplane under full and minimum loading conditions, to help the designer better understand the
performance of the VME device in this typical backplane. See www.ti.com/sc/etl for more information.
driver in slot 11, with receiver cards in all other slots (full load)
switching characteristics over recommended operating conditions for bus transceiver function
(unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN TYP
§
MAX UNIT
t
PLH
1A or 2A
1B or 2B
5.9 8.5
ns
t
PHL
1A or 2A
1B or 2B
5.5 8.7
ns
t
r
Transition time, B port (10%−90%)
9 8.6 11.4 ns
t
f
Transition time, B port (90%−10%)
8.9 9 10.8 ns
§
All typical values are at V
CC
= 3.3 V, T
A
= 25°C. All values are derived from TI-SPICE models.
All t
r
and t
f
times are taken at the first receiver.

        
        
SCES620 – DECEMBER 2004
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
driver in slot 11, with receiver cards in all other slots (full load) (continued)
switching characteristics over recommended operating conditions for UBT (unless otherwise
noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN TYP
†
MAX UNIT
t
PLH
3A
3B
6.2 8.9
ns
t
PHL
3A
3B
5.6 9
ns
t
PLH
LE
3B
6.1 9.1
ns
t
PHL
LE
3B
5.6 9
ns
t
PLH
CLKAB
3B
6.2 9.1
ns
t
PHL
CLKAB
3B
5.7 9
ns
t
r
‡
Transition time, B port (10%−90%)
9 8.6 11.4 ns
t
f
‡
Transition time, B port (90%−10%)
8.9 9 10.8 ns
†
All typical values are at V
CC
= 3.3 V, T
A
= 25°C. All values are derived from TI-SPICE models.
‡
All t
r
and t
f
times are taken at the first receiver.
skew characteristics for bus transceiver for specific worst-case V
CC
and temperature within the
recommended ranges of supply voltage and operating free-air temperature (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN TYP
†
MAX UNIT
t
sk(LH)
1A or 2A
1B or 2B
2.5
ns
t
sk(HL)
1A or 2A
1B or 2B
3
ns
t
sk(t)
§
1A or 2A 1B or 2B 1 ns
t
sk(pp)
1A or 2A 1B or 2B 0.5 3.4 ns
†
All typical values are at V
CC
= 3.3 V, T
A
= 25°C. All values are derived from TI-SPICE models.
§
t
sk(t)
− Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same
packaged device. The specifications are given for specific worst-case V
CC
and temperature and apply to any outputs switching in opposite
directions, both low to high (LH) and high to low (HL) [t
sk(t)
].
skew characteristics for UBT for specific worst-case V
CC
and temperature within the
recommended ranges of supply voltage and operating free-air temperature (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN TYP
†
MAX UNIT
t
sk(LH)
3A
3B
2.4
ns
t
sk(HL)
3A
3B
3.4
ns
t
sk(LH)
CLKAB
3B
2.7
ns
t
sk(HL)
CLKAB
3B
3.4
ns
t
sk(t)
§
3A 3B 1
ns
t
sk(t)
§
CLKAB 3B 1
ns
t
sk(pp)
3A 3B 0.5 3.4
ns
t
sk(pp)
CLKAB 3B 0.6 3.5
ns
†
All typical values are at V
CC
= 3.3 V, T
A
= 25°C. All values are derived from TI-SPICE models.
§
t
sk(t)
− Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same
packaged device. The specifications are given for specific worst-case V
CC
and temperature and apply to any outputs switching in opposite
directions, both low to high (LH) and high to low (HL) [t
sk(t)
].
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