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SN74VMEH22501ADGGR

Part # SN74VMEH22501ADGGR
Description Bus XCVR Single 10-CH 3-ST 48-Pin TSSOP T/R - Tape and Ree
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.


        
        
SCES620 – DECEMBER 2004
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
functional description for 8-bit UBT transceiver
The 3A and 3B data flow in each direction is controlled by the OE and direction-control (DIR) inputs. When OE
is low, all 3A- or 3B-port outputs are active. When OE is high, all 3A- or 3B-port outputs are in the high-impedance
state.
FUNCTION TABLE
INPUTS
OUTPUT
OE DIR
OUTPUT
H X Z
L H 3A data to 3B bus
L L 3B data to 3A bus
The UBT transceiver functions are controlled by latch-enable (LE) and clock (CLKAB and CLKBA) inputs. For
3A-to-3B data flow, the UBT operates in the transparent mode when LE is high. When LE is low, the 3A data
is latched if CLKAB is held at a high or low logic level. If LE is low, the 3A data is stored in the latch/flip-flop on
the low-to-high transition of CLKAB.
The UBT transceiver data flow for 3B to 3A is similar to that of 3A to 3B, but uses CLKBA.
UBT TRANSCEIVER FUNCTION TABLE
INPUTS
OUTPUT
MODE
OE LE CLKAB 3A
OUTPUT
3B
MODE
H X X X Z Isolation
L L H X B
0
Latched storage of 3A data
L LLXB
0
§
Latched storage of 3A data
L H X L L
True transparent
L HXHH
True transparent
L L L L
Clocked storage of 3A data
L L H H
Clocked storage of 3A data
3A-to-3B data flow is shown; 3B-to-3A data flow is similar, but uses CLKBA.
Output level before the indicated steady-state input conditions were established,
provided that CLKAB was high before LE went low
§
Output level before the indicated steady-state input conditions were established
The UBT transceiver can replace any of the functions shown in Table 1.
Table 1. SN74VMEH22501A UBT Transceiver Replacement Functions
FUNCTION 8 BIT
Transceiver ’245, ’623, ’645
Buffer/driver ’241, ’244, ’541
Latched transceiver ’543
Latch ’373, ’573
Registered transceiver ’646, ’652
Flip-flop ’374, ’574
SN74VMEH22501A UBT transceiver replaces all above functions

        
        
SCES620 – DECEMBER 2004
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
3B1
CLKAB
LE
CLKBA
3A1
To Seven Other Channels
OE
DIR
1OEAB
1OEBY
1A
1Y
2OEAB
2OEBY
2A
2Y
2B
1B
48
1
2
3
41
8
5
6
14
24
32
11
17
9
46
43
40
Pin numbers shown are for the DGG and DGV packages.

        
        
SCES620 – DECEMBER 2004
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
and BIAS V
CC
−0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, V
O
(see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Note 1): 3A port or Y output −0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port −0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current in the low state, I
O
: 3A port or Y output 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current in the high state, I
O
: 3A port or Y output −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port −100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
): B port −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DGG package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GQL package 42°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Notes 3 and 4)
MIN TYP MAX UNIT
V
CC
,
BIAS V
CC
Supply voltage 3.15 3.3 3.45 V
Input voltage
Control inputs or A port V
CC
5.5
V
V
I
Input voltage
B port
V
CC
5.5
V
High-level input voltage
Control inputs or A port 2
V
V
IH
High-level input voltage
B port
0.5 V
CC
+ 50 mV
V
Low-level input voltage
Control inputs or A port 0.8
V
V
IL
Low-level input voltage
B port
0.5 V
CC
− 50 mV
V
I
IK
Input clamp current −18 mA
High-level output current
3A port and Y output −12
mA
I
OH
High-level output current
B port
−48
mA
Low-level output current
3A port and Y output 12
mA
I
OL
Low-level output current
B port
64
mA
t/v Input transition rise or fall rate Outputs enabled 10 ns/V
t/V
CC
Power-up ramp rate 20 µs/V
T
A
Operating free-air temperature −40 85 °C
NOTES: 3. All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS V
CC
= 3.3 V first, I/O second, and
V
CC
= 3.3 V last, because the BIAS V
CC
precharge circuitry is disabled when any V
CC
pin is connected. The control inputs can be
connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence
is acceptable, but generally, GND is connected first.
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