Freelance Electronics Components Distributor
Closed Dec 25th-26th
800-300-1968
We Stock Hard to Find Parts

SN74LVT16543DL

Part # SN74LVT16543DL
Description Bus XCVR Dual 16-CH 3-ST 56-Pin SSOP Tube - Rail/Tube
Category IC
Availability In Stock
Qty 45
Qty Price
1 - 9 $6.76439
10 - 18 $5.38077
19 - 28 $5.07329
29 - 37 $4.71458
38 + $4.20212
Manufacturer Available Qty
Texas Instruments
  • Shipping Freelance Stock: 45
    Ships Immediately



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MAY 1992 – REVISED JULY 1995
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
Members of the Texas Instruments
Widebus
Family
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
CC
)
Support Unregulated Battery Operation
Down to 2.7 V
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25°C
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
Support Live Insertion
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes
PCB Layout
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’LVT16543 are 16-bit registered transceivers designed for low-voltage (3.3-V) V
CC
operation, but with the
capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or
OEBA
) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB
) input must be low in order to enter data from A or to output data from B. If CEAB
is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts
the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect
the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA,
LEBA, and OEBA inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Copyright 1995, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Widebus is a trademark of Texas Instruments Incorporated.
SN54LVT16543 . . . WD PACKAGE
SN74LVT16543 . . . DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEAB
1LEAB
1CEAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2CEAB
2LEAB
2OEAB
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MAY 1992 – REVISED JULY 1995
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT16543 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages,
which provide twice the I/O pin count and functionality of standard small-outline packages in the same
printed-circuit-board area.
The SN54LVT16543 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVT16543 is characterized for operation from –40°C to 85°C.
logic symbol
1A2
6
1A3
8
1A4
9
1A5
10
1A6
12
1A7
13
1A8
14
2A2
16
2A3
17
2A4
19
2A5
20
2A6
21
2A7
23
2A8
24
15
2A1
8C12
27
5
1A1
6D
1B6
45
1B7
44
1B8
43
1B2
51
1B3
49
1B4
48
1B5
47
1B1
52
5D
3
4
G8
26
8EN10
28
7C11
30
G7
31
7EN9
29
2C6
2
G2
3
2EN4
1
1C5
55
G1
54
1EN3
56
12D
2B6
36
2B7
34
2B8
33
2B2
41
2B3
40
2B4
38
2B5
37
2B1
42
11D
9
10
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MAY 1992 – REVISED JULY 1995
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A1
1B1
C1
1D
C1
1D
56
54
55
1
3
2
5
52
To Seven Other Channels
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A1
2B1
C1
1D
C1
1D
29
31
30
28
26
27
15
42
To Seven Other Channels
123NEXT