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SN74LVT162240DGGR

Part # SN74LVT162240DGGR
Description Buffer/Line Driver 16-CH Inverting 3-ST BiCMOS 48-Pin TSSO
Category IC
Availability In Stock
Qty 5
Qty Price
1 + $0.66446
Manufacturer Available Qty
Texas Instruments
Date Code: 0417
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

SN54LVT162240, SN74LVT162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS719 – JULY 2000
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Members of the Texas Instruments
Widebus
Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
Output Ports Have Equivalent 22- Series
Resistors, So No External Resistors Are
Required
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
CC
)
Support Unregulated Battery Operation
Down to 2.7 V
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C
I
off
and Power-Up 3-State Support Hot
Insertion
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR, and
the DGVR package is abbreviated to VR.
description
The ’LVT162240 devices are 16-bit buffers/drivers designed specifically for low-voltage (3.3-V) V
CC
operation
and to improve both the performance and density of 3-state memory address drivers, clock drivers, and
bus-oriented receivers and transmitters. They have the capability to provide a TTL interface to a 5-V system
environment.
These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer and provide inverting
outputs and symmetrical active-low output-enable (OE) inputs.
Copyright 2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
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48
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27
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25
1OE
1Y1
1Y2
GND
1Y3
1Y4
V
CC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
V
CC
4Y1
4Y2
GND
4Y3
4Y4
4OE
2OE
1A1
1A2
GND
1A3
1A4
V
CC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
V
CC
4A1
4A2
GND
4A3
4A4
3OE
SN54LVT162240 . . . WD PACKAGE
SN74LVT162240 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
SN54LVT162240, SN74LVT162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS719 – JULY 2000
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22- series resistors to
reduce overshoot and undershoot.
When V
CC
is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVT162240 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVT162240 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 4-bit buffer/driver)
INPUTS
OUTPUT
OE A
Y
L H L
L LH
H X Z
SN54LVT162240, SN74LVT162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS719 – JULY 2000
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic symbol
47
1A1
46
1A2
44
1A3
43
1A4
1Y1
2
1Y2
3
1Y3
5
1Y4
6
41
2A1
40
2A2
38
2A3
37
2A4
2Y1
8
2Y2
9
2Y3
11
2Y4
12
36
3A1
35
3A2
33
3A3
32
3A4
3Y1
13
3Y2
14
3Y3
16
3Y4
17
30
4A1
29
4A2
27
4A3
26
4A4
4Y1
19
4Y2
20
4Y3
22
4Y4
23
EN1
1
EN4
24
1OE
2OE
3OE
4OE
EN2
48
EN3
25
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12
13
14
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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