FEATURES
DESCRIPTION/ORDERING INFORMATION
DGG OR DGV PACKAGE
(TOP VIEW)
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1DIR
1B1
1B2
GND
1B3
1B4
V
CCB
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CCB
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
V
CCA
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CCA
2A5
2A6
GND
2A7
2A8
2OE
SN74LVCH16T245
16-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES635A – JULY 2005 – REVISED AUGUST 2005
• Control Inputs V
IH
/V
IL
Levels Are Referenced
to V
CCA
Voltage
• V
CC
Isolation Feature – If Either V
CC
Input Is at
GND, All Outputs Are in the High-Impedance
State
• Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
• Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.65-V to
5.5-V Power-Supply Range
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• I
off
Supports Partial-Power-Down Mode
Operation
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
This 16-bit noninverting bus transceiver uses two
separate configurable power-supply rails. The A port
is designed to track V
CCA
. V
CCA
accepts any supply
voltage from 1.65 V to 5.5 V. The B port is designed
to track V
CCB
. V
CCB
accepts any supply voltage from
1.65 V to 5.5 V. This allows for universal low-voltage
bidirectional translation between any of the 1.8-V,
2.5-V, 3.3-V, and 5-V voltage nodes.
The SN74LVCH16T245 is designed so that the control pins (1DIR, 2DIR, 1 OE, and 2 OE) are supplied by V
CCA
.
The SN74LVCH16T245 is designed for asynchronous communication between two data buses. The logic levels
of the direction-control (DIR) input and the output-enable ( OE) input activate either the B-port outputs or the
A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A
bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs
are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW
level applied to prevent excess I
CC
and I
CCZ
.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
TSSOP – DGG Tape and reel SN74LVCH16T245DGGR LVCH16T245
TVSOP – DGV Tape and reel SN74LVCH16T245DGVR LDHT245
–40 ° C to 85 ° C
VFBGA – GQL Tape and reel SN74LVCH16T245GQLR LDHT245
VFBGA – ZQL (Pb-free) Tape and reel SN74LVCH16T245ZQLR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
