SCES470A − AUGUST 2003 − REVISED AUGUST 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Available in the Texas Instruments
NanoStar and NanoFree Packages
D Supports 5-V V
CC
Operation
D Inputs Accept Voltages to 5.5 V
D Max t
pd
of 5.4 ns at 3.3 V
D Low Power Consumption, 10-µA Max I
CC
D ±24-mA Output Drive at 3.3 V
D Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C
D Typical V
OHV
(Output V
OH
Undershoot)
>2 V at V
CC
= 3.3 V, T
A
= 25°C
D I
off
Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This triple Schmitt-trigger buffer is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC3G17 contains three buffers, and performs the Boolean function Y = A. The device functions as
three independent buffers, but because of Schmitt action, it may have different input threshold levels for
positive-going (V
T+
) and negative-going (V
T−
) signals.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
SN74LVC3G17YEPR
−40°C to 85°C
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
Tape and reel
SN74LVC3G17YZPR
_ _ _C7_
SSOP − DCT Tape and reel SN74LVC3G17DCTR C17_ _ _
VSSOP − DCU Tape and reel SN74LVC3G17DCUR C17_
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb,
• = Pb-free).
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
(TOP VIEW)
1
2
3
4
8
7
6
5
1A
3Y
2A
GND
V
CC
1Y
3A
2Y
4
3
2
1
5
6
7
8
GND
2A
3Y
1A
2Y
3A
1Y
V
CC
YEP OR YZP PACKAGE
(BOTTOM VIEW)
NanoStar and NanoFree are trademarks of Texas Instruments.
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