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SN74LV4052ADR

Part # SN74LV4052ADR
Description DUAL ANALOG MULTIPLXR/DEMULTIPLXR - Tape and Reel
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

 
   
SCLS429H − MAY 1999 − REVISED APRIL 2005
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D 2-V to 5.5-V V
CC
Operation
D Support Mixed-Mode Voltage Operation on
All Ports
D Fast Switching
D High On-Off Output-Voltage Ratio
D Low Crosstalk Between Switches
D Extremely Low Input Current
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
These dual 4-channel CMOS analog
multiplexers/demultiplexers are designed for 2-V
to 5.5-V V
CC
operation.
The ’LV4052A devices handle both analog and
digital signals. Each channel permits signals with
amplitudes up to 5.5 V (peak) to be transmitted in
either direction.
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing for analog-to-digital and digital-to-
analog conversion systems.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N Tube of 25 SN74LV4052AN SN74LV4052AN
QFN − RGY Reel of 1000 SN74LV4052ARGYR LW052A
SOIC − D
Tube of 40 SN74LV4052AD
LV4052A
SOIC − D
Reel of 2500 SN74LV4052ADR
LV4052A
−40°C to 85°C
SOP − NS Reel of 2000 SN74LV4052ANSR 74LV4052A
−40°C to 85°C
SSOP − DB Reel of 2000 SN74LV4052ADBR LW052A
Tube of 90 SN74LV4052APW
TSSOP − PW
Reel of 2000 SN74LV4052APWR
LW052A
TSSOP − PW
Reel of 250 SN74LV4052APWT
LW052A
TVSOP − DGV Reel of 2000 SN74LV4052ADGVR LW052A
−55°C to 125°C
CDIP − J Tube of 25 SNJ54LV4052AJ SNJ54LV4052AJ
−55
°
C to 125
°
C
CFP − W Tube of 150 SNJ54LV4052AW SNJ54LV4052AW
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright 2005, Texas Instruments Incorporated
    !"#$%&' #"'(' 
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+(*(%&&*.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Y0
2Y2
2-COM
2Y3
2Y1
INH
GND
GND
V
CC
1Y2
1Y1
1-COM
1Y0
1Y3
A
B
SN54LV4052A ...J OR W PACKAGE
SN74LV4052A . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
SN74LV4052A . . . RGY PACKAGE
(TOP VIEW)
116
89
2
3
4
5
6
7
15
14
13
12
11
10
1Y2
1Y1
1-COM
1Y0
1Y3
A
2Y2
2-COM
2Y3
2Y1
INH
GND
2Y0
B
V
GND
CC
 
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SCLS429H − MAY 1999 − REVISED APRIL 2005
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
ON
INH B A
ON
CHANNEL
L L L 1Y0, 2Y0
L L H 1Y1, 2Y1
L H L 1Y2, 2Y2
L H H 1Y3, 2Y3
H X X None
logic diagram (positive logic)
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
1-COM
INH
B
A
2-COM
10
9
6
13
12
14
15
11
1
5
2
4
3
 
   
SCLS429H − MAY 1999 − REVISED APRIL 2005
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
−0.5 V to 7.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) −0.5 V to 7.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch I/O voltage range, V
IO
(see Notes 1 and 2) −0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O diode current, I
IOK
(V
IO
< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch through current, I
T
(V
IO
= 0 to V
CC
) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 4): RGY package 39°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 5)
SN54LV4052A SN74LV4052A
UNIT
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 2
5.5 2
5.5 V
V
CC
= 2 V 1.5 1.5
V
IH
High-level input voltage,
V
CC
= 2.3 V to 2.7 V V
CC
× 0.7 V
CC
× 0.7
V
V
IH
High-level input voltage,
control inputs
V
CC
= 3 V to 3.6 V
V
CC
× 0.7 V
CC
× 0.7
V
control inputs
V
CC
= 4.5 V to 5.5 V V
CC
× 0.7 V
CC
× 0.7
V
CC
= 2 V 0.5 0.5
V
IL
Low-level input voltage,
V
CC
= 2.3 V to 2.7 V V
CC
× 0.3 V
CC
× 0.3
V
V
IL
Low-level input voltage,
control inputs
V
CC
= 3 V to 3.6 V
V
CC
× 0.3 V
CC
× 0.3
V
control inputs
V
CC
= 4.5 V to 5.5 V V
CC
× 0.3 V
CC
× 0.3
V
I
Control input voltage 0 5.5 0 5.5 V
V
IO
Input/output voltage 0 V
CC
0 V
CC
V
V
CC
= 2.3 V to 2.7 V 200 200
t/v Input transition rise or fall rate
V
CC
= 3 V to 3.6 V
100 100
ns/V
t/v
Input transition rise or fall rate
V
CC
= 4.5 V to 5.5 V 20 20
ns/V
T
A
Operating free-air temperature −55 125 −40 85 °C
With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals
be transmitted at these low supply voltages.
NOTE 5: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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