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SN74HC138N

Part # SN74HC138N
Description 3 TO 8 LINE DECODER/DEMUX
Category IC
Availability In Stock
Qty 48
Qty Price
1 - 10 $1.14438
11 - 20 $0.91550
21 - 30 $0.75529
31 - 40 $0.70189
41 + $0.62559
Manufacturer Available Qty
NXP SEMICONDUCTORS
Date Code: 0906
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

 
   
SCLS107E − DECEMBER 1982 − REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Targeted Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max I
CC
D Typical t
pd
= 15 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception
description/ordering information
The ’HC138 devices are designed to be used in
high-performance memory-decoding or data-
routing applications requiring very short
propagation delay times. In high-performance
memory systems, these decoders can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of these
decoders and the enable time of the memory are
usually less than the typical access time of the
memory. This means that the effective system
delay introduced by the decoders is negligible.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N Tube of 25 SN74HC138N SN74HC138N
Tube of 40 SN74HC138D
SOIC − D
Reel of 2500 SN74HC138DR
HC138
SOIC − D
Reel of 250 SN74HC138DT
HC138
−40°C to 85°C
SOP − NS Reel of 2000 SN74HC138NSR HC138
−40 C to 85 C
SSOP − DB Reel of 2000 SN74HC138DBR HC138
Tube of 90 SN74HC138PW
TSSOP − PW
Reel of 2000 SN74HC138PWR
HC138
TSSOP − PW
Reel of 250 SN74HC138PWT
HC138
CDIP − J Tube of 25 SNJ54HC138J SNJ54HC138J
−55°C to 125°C
CFP − W Tube of 150 SNJ54HC138W SNJ54HC138W
−55 C to 125 C
LCCC − FK Tube of 55 SNJ54HC138FK SNJ54HC138FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
3212019
910111213
4
5
6
7
8
18
17
16
15
14
Y1
Y2
NC
Y3
Y4
C
G
2A
NC
G
2B
G1
B
A
NC
Y6
Y5
V
Y0
Y7
GND
NC
SN54HC138 . . . FK PACKAGE
(TOP VIEW)
CC
NC − No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
B
C
G
2A
G
2B
G1
Y7
GND
V
CC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
SN54HC138 ...J OR W PACKAGE
SN74HC138 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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"&#"0  !)) '!!&"&#+
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   
SCLS107E − DECEMBER 1982 − REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description/ordering information (continued)
The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
FUNCTION TABLE
INPUTS
OUTPUTS
ENABLE SELECT
OUTPUTS
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X X H H H H H H H H
X XHXXXHHHHHHHH
L XXXXXHHHHHHHH
H LLLLLLHHHHHHH
H LLLLHHLHHHHHH
H LLLHLHHLHHHHH
H LLLHHHHHLHHHH
H LLHLLHHHHLHHH
H LLHLHHHHHHLHH
H LLHHLHHHHHHLH
H L L H H H H H H H H H H L
 
   
SCLS107E − DECEMBER 1982 − REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
B
C
G1
G2A
G2B
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
1
2
3
6
4
5
15
14
13
12
11
10
9
7
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
−0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
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