Freelance Electronics Components Distributor
Closed Dec 25th-26th
800-300-1968

We Stock Hard to Find Parts
My Account | My Orders | My Cart
Questions? (800) 300-1968

SN74CBTLV3251D

Part # SN74CBTLV3251D
Description Multiplexer/Demultiplexer BusSwitch 1-Element CMOS 8-IN 1
Category IC
Availability In Stock
Qty 38
Qty Price
1 + $0.32087
Manufacturer Available Qty
Texas Instruments
Date Code: 0014
  • Shipping Freelance Stock: 38
    Ships Immediately

Related Items

SN74CB3Q16211ZQLR
Texas Instruments
IC
SN74CB3Q16211ZQLR
$1.63017
SN74CB3T3125PWR
Texas Instruments
IC
SN74CB3T3125PWR
$0.42396
SN74CBT16232DGGR
Texas Instruments
IC
SN74CBT16232DGGR
$0.73013
SN74CBT1G125DBVR
Texas Instruments
IC
SN74CBT1G125DBVR
$0.06979
SN74CBT32245GKER
Texas Instruments
IC
SN74CBT32245GKER
$3.32922
SN74CBT3257DB
Texas Instruments
IC
SN74CBT3257DB
$1.87431


Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.


   
SCDS054I − MARCH 1998 − REVISED OCTOBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D 5-Ω Switch Connection Between Two Ports
D Rail-to-Rail Switching on Data I/O Ports
D I
off
Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B4
B3
B2
B1
A
NC
OE
GND
V
CC
B5
B6
B7
B8
S0
S1
S2
D, DBQ, DGV, OR PW PACKAGE
(TOP VIEW)
NC − No internal connection
RGY PACKAGE
(TOP VIEW)
116
89
2
3
4
5
6
7
15
14
13
12
11
10
B5
B6
B7
B8
S0
S1
B3
B2
B1
A
NC
OE
B4
S2
V
GND
CC
NC − No internal connection
description/ordering information
The SN74CBTLV3251 device is a 1-of-8 high-speed FET multiplexer/demultiplexer. The low on-state resistance
of the switch allows connections to be made with minimal propagation delay.
The select inputs (S0, S1, S2) control the data flow. The FET multiplexers/demultiplexers are disabled when
the output-enable (OE) input is high.
This device is fully specified for partial-power-down applications using I
off
. The I
off
feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY Tape and reel SN74CBTLV3251RGYR CL251
SOIC − D
Tube SN74CBTLV3251D
CBTLV3251
−40°C to 85°C
SOIC − D
Tape and reel SN74CBTLV3251DR
CBTLV3251
−40°C to 85°C
SSOP (QSOP) − DBQ Tape and reel SN74CBTLV3251DBQR CL251
TSSOP − PW Tape and reel SN74CBTLV3251PWR CL251
TVSOP − DGV Tape and reel SN74CBTLV3251DGVR CL251
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
  !"#$%&" ' ()##*& %' "! +),-(%&" .%&*/
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&'
'&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).*
&*'&4 "! %-- +%#%$*&*#'/

   
SCDS054I − MARCH 1998 − REVISED OCTOBER 2003
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
FUNCTION
OE S2 S1 S0
FUNCTION
L L L L A port = B1 port
L L L H A port = B2 port
L L H L A port = B3 port
L L H H A port = B4 port
L H L L A port = B5 port
L H L H A port = B6 port
L H H L A port = B7 port
L H H H A port = B8 port
H X X X Disconnect
logic diagram (positive logic)
B5
B1
A
S0
S1
S2
OE
B2
B3
B4
B6
B7
B8
SW
SW
SW
SW
SW
SW
SW
SW
5
11
10
9
7
4
3
2
1
15
14
13
12

   
SCDS054I − MARCH 1998 − REVISED OCTOBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
simplified schematic, each FET switch
A
(OE)
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
−0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) −0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
K
(V
I/O
< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DBQ package 90°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package 39°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
CC
Supply voltage 2.3 3.6 V
V
IH
High-level control input voltage
V
CC
= 2.3 V to 2.7 V 1.7
V
IH
High-level control input voltage
V
CC
= 2.7 V to 3.6 V
2
V
V
IL
Low-level control input voltage
V
CC
= 2.3 V to 2.7 V 0.7
V
IL
Low-level control input voltage
V
CC
= 2.7 V to 3.6 V
0.8
V
T
A
Operating free-air temperature −40 85 °C
NOTE 4: All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
1234NEXT
Address
Freelance Electronics
13197 Sandoval Street
Santa Fe Springs, CA 90670
 
Hours of Operation  (Holiday Hours)
Monday-Friday 7:30am-4:30pm PST
(Deadline for next day shipment 2:00pm PST)
Seal
Government Cage code#-1V4R6
Duns Number# 788130532
Certified Small Disadvantaged Business
Customer Service
Company
Information
Connect with Us
Twitter Facebook Instagra,
This site is protected by Trustwave's Trusted Commerce program