Name: SN74CBTLV16210VR
SKU: SN74CBTLV16210VR
Price: 0.96537 USD
Availability: InStock



    

SCDS042J − DECEMBER 1997 − REVISED JULY 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Member of the Texas Instruments

Widebus Family

D 5-Ω Switch Connection Between Two Ports

D Rail-to-Rail Switching on Data I/O Ports

D I

off

Supports Partial-Power-Down Mode

Operation

description/ordering information

The SN74CBTLV16210 provides 20 bits of

high-speed bus switching. The low on-state

resistance of the switch allows connections to be

made with minimal propagation delay.

The device is organized as dual 10-bit bus

switches with separate output-enable (OE

)

inputs. It can be used as two 10-bit bus switches

or as one 20-bit bus switch. When OE

is low, the

associated 10-bit bus switch is on, and port A is

connected to port B. When OE

is high, the switch

is open, and the high-impedance state exists

between the two ports.

This device is fully specified for

partial-power-down applications using I

off

. The I

off

feature ensures that damaging current will not

backflow through the device when it is powered

down. The device has isolation during power off.

To ensure the high-impedance state during power

up or power down, OE

should be tied to V

through a pullup resistor; the minimum value of

the resistor is determined by the current-sinking

capability of the driver.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SSOP − DL

Tube SN74CBTLV16210DL

CBTLV16210

−40°C to 85°C

SSOP − DL

Tape and reel SN74CBTLV16210DLR

CBTLV16210

−40 C to 85 C

TVSOP − DGV Tape and reel SN74CBTLV16210VR CN210

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

FUNCTION TABLE

(each 10-bit bus switch)

INPUT

FUNCTION

L A port = B port

H Disconnect

  !"# $ %&'# "$  (&)*%"# +"#',

+&%#$ %! # $('%%"#$ (' #-' #'!$  '."$ $#&!'#$

$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'

#'$#1  "** (""!'#'$,

DGV OR DL PACKAGE

(TOP VIEW)

1A1

1A2

1A3

1A4

1A5

1A6

GND

1A7

1A8

1A9

1A10

2A1

2A2

2A3

GND

2A4

2A5

2A6

2A7

2A8

2A9

2A10

1OE

2OE

1B1

1B2

1B3

1B4

1B5

GND

1B6

1B7

1B8

1B9

1B10

2B1

2B2

2B3

GND

2B4

2B5

2B6

2B7

2B8

2B9

2B10

NC − No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.



    

SCDS042J − DECEMBER 1997 − REVISED JULY 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1A1

1B1

1A10

1OE

1B10

2A1

2B1

2A10

2OE

2B10

simplified schematic, each FET switch

(OE)

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

−0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(see Note 1) −0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 2): DGV package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 63°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.



    

SCDS042J − DECEMBER 1997 − REVISED JULY 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

MIN MAX UNIT

Supply voltage 2.3 3.6 V

High-level control input voltage

= 2.3 V to 2.7 V 1.7

High-level control input voltage

= 2.7 V to 3.6 V

Low-level control input voltage

= 2.3 V to 2.7 V 0.7

Low-level control input voltage

= 2.7 V to 3.6 V

0.8

Operating free-air temperature −40 85 °C

NOTE 3: All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

†

MAX UNIT

= 3 V, I

= −18 mA −1.2 V

= 3.6 V, V

= V

or GND ±1 µA

off

= 0, V

or V

= 0 to 3.6 V 10 µA

= 3.6 V, I

= 0, V

= V

or GND 10 µA

∆I

‡

Control inputs V

= 3.6 V, One input at 3 V, Other inputs at V

or GND 300 µA

Control inputs V

= 3 V or 0 4.5 pF

io(OFF)

= 3 V or 0, OE = V

6.5 pF

= 2.3 V,

= 0

= 64 mA 5 8

= 2.3 V,

TYP at V

= 2.5 V

= 0

= 24 mA 5 8

TYP at V

= 2.5 V

= 1.7 V, I

= 15 mA 27 40

Ω

= 0

= 64 mA 5 7

Ω

= 3 V

= 0

= 24 mA 5 7

= 3 V

= 2.4 V, I

= 15 mA 10 15

†

All typical values are at V

= 3.3 V (unless otherwise noted), T

= 25°C.

‡

This is the increase in supply current for each input that is at the specified voltage level, rather than V

or GND.

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by

the lower of the voltages of the two (A or B) terminals.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 1)

PARAMETER

FROM

(INPUT)

(OUTPUT)

= 2.5 V

± 0.2 V

= 3.3 V

± 0.3 V

UNIT

PARAMETER

(INPUT)

(OUTPUT)

MIN MAX MIN MAX

UNIT

A or B B or A 0.15 0.25 ns

OE A or B 1 6.8 1 6 ns

dis

OE A or B 1 7.3 1 7.4 ns

The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when

driven by an ideal voltage source (zero output impedance).

Part #	SN74CBTLV16210VR
Description	20 BIT FET BUS SWITCH, TVSOP-48, FULL REEL, No. of Channel
Category	IC
Availability	In Stock
Qty	2

Manufacturer	Available	Qty
Texas Instruments	Freelance Stock: 1 Ships Immediately
Texas Instruments	Freelance Stock: 1 Ships Immediately

SN74CBTLV16210VR

Related Items

Technical Document