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SN74AS181ANT

Part # SN74AS181ANT
Description 4 BIT ALU/FUNCTION GENERATOR,21NS DIP24, Supply Voltage M
Category IC
Availability In Stock
Qty 9
Qty Price
1 - 1 $13.08734
2 - 3 $10.41038
4 - 5 $9.81550
6 - 7 $9.12148
8 + $8.13001
Manufacturer Available Qty
Texas Instruments
Date Code: 8205
  • Shipping Freelance Stock: 4
    Ships Immediately
Texas Instruments
Date Code: 8204
  • Shipping Freelance Stock: 5
    Ships Immediately

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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

SN54AS181B, SN74AS181A
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
SDAS209B – DECEMBER 1982 – REVISED DECEMBER 1994
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram
C
n
A
0
A
1
A
2
A
3
B
0
B
1
B
2
B
3
P
G
C
n
+
4
F
0
F
1
F
2
F
3
S3
S2
S1
S0
M
3
4
5
6
18
19
20
21
22
23
1
2
8
7
A = B
17
16
15
13
11
14
10
9
Pin numbers shown are for the JT, JW, N, and NT packages.
SN54AS181B, SN74AS181A
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
SDAS209B – DECEMBER 1982 – REVISED DECEMBER 1994
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
signal designations
In Figures 1 and 2, the polarity indicators ( ) indicate that the associated input or output is active low with
respect to the function shown inside the symbol. The symbols are the same in both figures. The signal
designations in Figure 1 agree with the indicated internal functions based on active-low data and are for use
with the logic functions and arithmetic operations shown in Table 1. The signal designations have been changed
in Figure 2 to accommodate the logic functions and arithmetic operations for the active-high data given in
Table 2. The SN54AS181B and SN74AS181A together with the ′S182 can be used with the signal designation
of either Figure 1 or Figure 2.
M
0
31
0
6
S0
5
S1
4
S2
3
S3
4
8
M
15
A = B
14
C1
7
17
16
9
10
11
13
P
2
Q
1
P
23
Q
22
P
21
Q
20
P
19
Q
18
ALU
[1]
[2]
[3]
[8]
C
n
A
0
A
1
A2
A
3
B0
B
1
B2
B
3
(0 . . . 15) CP
(0 . . . 15) CG
6(P=Q)
(0 . . . 15) CO
P
G
C
n
+
4
F0
F
1
F
2
F
3
SN54AS181B,
SN74AS181A
M
0
31
0
6
S0
5
S1
4
S2
3
S3
4
8
M
15
A = B
14
7
17
16
F0
9
F1
10
F2
11
F3
13
P
2
Q
1
P
23
Q
22
P
21
Q
20
P
19
Q
18
ALU
[1]
[2]
[3]
[8]
C
n
A
0
A
1
A2
A
3
B0
B
1
B2
B
3
(0 . . . 15) CP
(0 . . . 15) CG
6(P=Q)
(0 . . . 15) CO
X
Y
C
n
+
4
SN54AS181B,
SN74AS181A
CP0
3
CG0
2
CPG
CP1
5
CG1
4
CP2
8
CG2
7
CP3
10
CG3
9
CP4
14
CG4
13
CP5
16
CG5
15
CP6
19
CG6
18
CP7
21
CG7
20
1
6
CO1
11
CO3
17
CO5
22
CO7
C
n
P
0
G0
P
1
G1
P
2
G2
P3
G3
P4
G4
P5
G5
P
6
G6
P
7
G7
′S182
C
n
+
8
C
n
+
16
C
n
+
24
C
n
+
32
C1
CP0
3
CG0
2
CPG
CP1
5
X1
CG1
4
Y1
CP2
8
X2
CG2
7
Y2
CP3
10
X3
CG3
9
Y3
CP4
14
X4
CG4
13
Y4
CP5
16
X5
CG5
15
Y5
CP6
19
X6
CG6
18
Y6
CP7
21
X7
CG7
20
Y7
1
6
CO1
11
CO3
17
CO5
22
CO7
C
n
X0
Y0
′S182
C
n
+
8
C
n
+
16
C
n
+
24
C
n
+
32
Figure 1 Figure 2
(use with Table 1) (use with Table 2)
SN54AS181B, SN74AS181A
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
SDAS209B – DECEMBER 1982 – REVISED DECEMBER 1994
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 1
SELECTION
ACTIVE-LOW DATA
SELECTION
M = H
M = L; ARITHMETIC OPERATIONS
S3 S2 S1 S0
LOGIC
FUNCTIONS
C
n
= L
(no carry)
C
n
= H
(with carry)
L L L L F = A F = A MINUS 1 F = A
L L L H F = AB F = AB MINUS 1 F = AB
L L H L F = A + B F = AB MINUS 1 F = AB
L L H H F = 1 F = MINUS 1 (2’s COMP) F = ZERO
L H L L F = A + B F = A PLUS (A + B) F = A PLUS (A + B) PLUS 1
L H L H F = B F = AB PLUS (A + B) F = AB PLUS (A + B) PLUS 1
L H H L F = A ⊕ B F = A MINUS B MINUS 1 F = A MINUS B
L H H H F = A + B F = A + B F = (A + B) PLUS 1
H L L L F = AB F = A PLUS (A + B) F = A PLUS (A + B) PLUS 1
H L L H F = A ⊕ B F = A PLUS B F = A PLUS B PLUS 1
H L H L F = B F = AB PLUS (A + B) F = AB PLUS (A + B) PLUS 1
H L H H F = A + B F = (A + B) F = (A + B) PLUS 1
H H L L F = 0 F = A PLUS A
†
F = A PLUS A PLUS 1
H H L H F = AB F = AB PLUS A F = AB PLUS A PLUS 1
H H H L F = AB F = AB PLUS A F =AB PLUS A PLUS 1
H H H H F = A F = A PLUS 1 F = A PLUS 1
†
Each bit is shifted to the next more significant position.
Table 2
SELECTION
ACTIVE-HIGH DATA
SELECTION
M = H
M = L; ARITHMETIC OPERATIONS
S3 S2 S1 S0
LOGIC
FUNCTIONS
C
n
= H
(no carry)
C
n
= L
(with carry)
L L L L F = A F = A F = A PLUS 1
L L L H F = A + B F = A + B F = (A+ B) PLUS 1
L L H L F = AB F = A + B F = (A + B) PLUS 1
L L H H F = 0 F = MINUS 1 (2’s COMPL) F = ZERO
L H L L F = AB F = A PLUS AB F = A PLUS AB PLUS 1
L H L H F = B F = (A + B) PLUS AB F =( A + B) PLUS AB PLUS 1
L H H L F = A ⊕ B F = A MINUS B MINUS 1 F = A MINUS B
L H H H F = AB F = AB MINUS 1 F = A B
H L L L F = A + B F = A PLUS AB F = A PLUS AB PLUS 1
H L L H F = A ⊕ B F = A PLUS B F = A PLUS B PLUS 1
H L H L F = B F = (A + B) PLUS AB F = (A + B) PLUS AB PLUS 1
H L H H F = AB F = AB MINUS 1 F = AB
H H L L F = 1 F = A PLUS A
†
F = A PLUS A PLUS 1
H H L H F = A + B F = (A + B) PLUS A F = (A + B) PLUS A PLUS 1
H H H L F = A + B F = (A + B) PLUS A F =(A + B) PLUS A PLUS 1
H H H H F = A F = A MINUS 1 F = A
†
Each bit is shifted to the next more significant position.
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