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SN74ALS373AN

Part # SN74ALS373AN
Description OCTAL D-TYPE LATCH - Rail/Tube
Category IC
Availability In Stock
Qty 32
Qty Price
1 + $0.31854
Manufacturer Available Qty
Texas Instruments
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS083C – APRIL 1982 – REVISED MARCH 2002
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Eight Latches in a Single Package
3-State Bus-Driving True Outputs
Full Parallel Access for Loading
Buffered Control Inputs
pnp Inputs Reduce dc Loading on Data
Lines
description
These octal transparent D-type latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
A buffered output-enable (OE
) input can be used
to place the eight outputs in either a normal logic
state (high or low) or a high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and the increased drive
provide the capability to drive bus lines without
interface or pullup components.
OE
does not affect internal operations of the
latches. Old data can be retained or new data can
be entered while the outputs are off.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
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13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
SN54ALS373A, ...J OR W PACKAGE
SN54AS373 ...J PACKAGE
SN74ALS373A, SN74AS373 ...DW, N, OR NS PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
SN54ALS373A, SN54AS373 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OE
5Q
5D 8Q
4Q
GND
LE
V
CC
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS083C APRIL 1982 REVISED MARCH 2002
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube
SN74ALS373AN SN74ALS373AN
PDIP
N
Tube
SN74AS373N SN74AS373N
Tube SN74ALS373ADW
ALS373A
0°Cto70°C
SOIC DW
Tape and reel SN74ALS373ADWR
ALS373A
0°C
to
70°C
SOIC
DW
Tube SN74AS373DW
AS373
Tape and reel SN74AS373DWR
AS373
SOP NS
Ta
p
e and reel
SN74ALS373ANSR ALS373A
SOP
NS
Tape
and
reel
SN74AS373NSR 74AS373
CDIP J
Tube
SNJ54ALS373AJ SNJ54ALS373AJ
CDIP
J
Tube
SNJ54AS373J SNJ54AS373J
55°C to 125°C
CFP W Tube SNJ54ALS373AW SNJ54ALS373AW
LCCC FK
Tube
SNJ54ALS373AFK SNJ54ALS373AFK
LCCC
FK
Tube
SNJ54AS373FK SNJ54AS373FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE LE D
Q
L H H H
L HL L
L LX Q
0
H X X Z
logic diagram (positive logic)
OE
LE
1D
1Q
1
11
3
2
To Seven Other Channels
C1
1D
SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SDAS083C APRIL 1982 REVISED MARCH 2002
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (SN54ALS373A,
SN74ALS373A) (unless otherwise noted)
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any output in the high state or power-off state 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 1): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54ALS373A SN74ALS373A
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.7 0.8 V
I
OH
High-level output current 1 2.6 mA
I
OL
Low-level output current 12 24 mA
T
A
Operating free-air temperature 55 125 0 70 °C
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ALS373A SN74ALS373A
UNIT
MIN MAX MIN MAX
UNIT
f
clock
Clock frequency MHz
t
w
Pulse duration, LE high 12 10 ns
t
su
Setup time, data before LE 10 10 ns
t
h
Hold time, data after LE 7 7 ns
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