SN54ALS259, SN74ALS259
8-BIT ADDRESSABLE LATCHES
SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994
Copyright 1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• 8-Bit Parallel-Out Storage Register
Performs Serial-to-Parallel Conversion With
Storage
• Asynchronous Parallel Clear
• Active-High Decoder
• Enable/Disable Input Simplifies Expansion
• Expandable for n-Bit Applications
• Four Distinct Functional Modes
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These 8-bit addressable latches are designed for
general-purpose storage applications in digital
systems. Specific uses include working registers,
serial-holding registers, and active-high decoders
or demultiplexers. They are multifunctional
devices capable of storing single-line data in eight
addressable latches and being a 1-of-8 decoder or
demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by
controlling the clear (CLR
) and enable (G) inputs
as shown in the function table. In the
addressable-latch mode, data at the data-in
terminal is written into the addressed latch. The
addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the
memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To
eliminate the possibility of entering erroneous data in the latches, G
should be held high (inactive) while the
address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the
level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address
and data inputs.
The SN54ALS259 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ALS259 is characterized for operation from 0°C to 70°C.
Function Tables
FUNCTION
INPUTS
OUTPUT OF
EACH
CLR G
LATCH
OUTPUT
H L D Q
iO
Addressable latch
H HQ
iO
Q
iO
Memory
L LD L8-line demultiplexer
L H L L Clear
D = the level at the data input.
Q
iO
= the level of Q
i
(i = Q, 1,...7 as appropriate) before the indicated
steady-state input conditions were established.
SN54ALS259 ...J PACKAGE
SN74ALS259 ...D OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
G
D
NC
Q7
Q6
S2
Q0
NC
Q1
Q2
SN54ALS259 . . . FK PACKAGE
(TOP VIEW)
S1
S0
NC
Q4
Q5
CLR
Q3
GND
NC
NC – No internal connection
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S0
S1
S2
Q0
Q1
Q2
Q3
GND
V
CC
CLR
G
D
Q7
Q6
Q5
Q4
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
