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SN74AHC595PWR

Part # SN74AHC595PWR
Description 8 BIT SHIFT REGISTER W/3-ST OUT REGT - Tape and Reel
Category IC
Availability In Stock
Qty 232
Qty Price
1 - 48 $0.18597
49 - 97 $0.14793
98 - 146 $0.13948
147 - 194 $0.12962
195 + $0.11553
Manufacturer Available Qty
Texas Instruments
Date Code: 0714
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

 
  
   
SCLS373I − MAY 1997 − REVISED JUNE 2004
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Operating Range 2-V to 5.5-V V
CC
D 8-Bit Serial-In, Parallel-Out Shift
D Shift Register Has Direct Clear
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
The ’AHC595 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel
3-state outputs. Separate clocks are provided for
both the shift and storage registers. The shift
register has a direct overriding clear (SRCLR
)
input, serial (SER) input, and a serial output for
cascading. When the output-enable (OE
) input is
high, all outputs, except Q
H
, are in the
high-impedance state.
Both the shift-register clock (SRCLK) and
storage-register clock (RCLK) are positive-edge
triggered. If both clocks are connected together,
the shift register always is one clock pulse ahead
of the storage register.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N Tube SN74AHC595N SN74AHC595N
SOIC − D
Tube SN74AHC595D
AHC595
SOIC − D
Tape and reel SN74AHC595DR
AHC595
−40°C to 85°C
SOP − NS Tape and reel SN74AHC595NSR AHC595
−40 C to 85 C
SSOP − DB Tape and reel SN74AHC595DBR HA595
TSSOP − PW
Tube SN74AHC595PW
HA595
TSSOP − PW
Tape and reel SN74AHC595PWR
HA595
CDIP − J Tube SNJ54AHC959J SNJ54AHC595J
−55°C to 125°C
CFP − W Tube SNJ54AHC595W SNJ54AHC595W
−55 C to 125 C
LCCC − FK Tube SNJ54AHC595FK SNJ54AHC595FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright 2004, Texas Instruments Incorporated
    !"#$%& "!&'& 
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*%"("'!& *%) % %)$ !( %.' &)#$%& '&') /'))'&0-
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*')'$%%)-
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54AHC595 ...J OR W PACKAGE
SN74AHC595 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54AHC595 . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
GND
V
CC
Q
A
SER
OE
RCLK
SRCLK
SRCLR
Q
H
3212019
910111213
4
5
6
7
8
18
17
16
15
14
SER
OE
NC
RCLK
SRCLK
Q
D
Q
E
NC
Q
F
Q
G
Q
NC
SRCLR
H
GND
NC
C
Q
B
V
CC
Q
A
Q
H
Q
 
  
   
SCLS373I − MAY 1997 − REVISED JUNE 2004
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
FUNCTION
SER SRCLK SRCLR RCLK OE
FUNCTION
X X X X H Outputs Q
A
−Q
H
are disabled.
X X X X L Outputs Q
A
−Q
H
are enabled.
X X L X X Shift register is cleared.
L H X X
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H H X X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
X X X X Shift-register data is stored into the storage register.
 
  
   
SCLS373I − MAY 1997 − REVISED JUNE 2004
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
3D
C3
1D
C1
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
3D
C3
2D
C2
R
13
12
10
11
14
15
1
2
3
4
5
6
7
9
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Q
H
OE
SRCLR
RCLK
SRCLK
SER
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
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