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SN74AHC02PWR

Part # SN74AHC02PWR
Description NOR Gate 4-Element 2-IN CMOS14-Pin TSSOP T/R - R01
Category IC
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Texas Instruments
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

SN54AHC02, SN74AHC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS254K– DECEMBER 1995 – REVISED JULY 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Operating Range 2-V to 5.5-V V
CC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1Y
1A
1B
2Y
2A
2B
GND
V
CC
4Y
4B
4A
3Y
3B
3A
SN54AHC02 ...J OR W PACKAGE
SN74AHC02 . . . D, DB, DGV, N, NS
OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4B
NC
4A
NC
3Y
1B
NC
2Y
NC
2A
1A
1Y
NC
3A
3B
V
4Y
2B
GND
NC
SN54AHC02 . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
SN74AHC02 . . . RGY PACKAGE
(TOP VIEW)
114
78
2
3
4
5
6
13
12
11
10
9
4Y
4B
4A
3Y
3B
1A
1B
2Y
2A
2B
1Y
3A
V
GND
CC
description/ordering information
The ’AHC02 devices contain four independent 2-input NOR gates that perform the Boolean function
Y = A
B or Y = A + B in positive logic.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN – RGY Tape and reel SN74AHC02RGYR HA02
PDIP – N Tube SN74AHC02N SN74AHC02N
SOIC – D
Tube SN74AHC02D
AHC02
SOIC
–
D
Tape and reel SN74AHC02DR
AHC02
–40°C to 85°C
SOP – NS Tape and reel SN74AHC02NSR AHC02
SSOP – DB Tape and reel SN74AHC02DBR HA02
TSSOP PW
Tube SN74AHC02PW
HA02
TSSOP
–
PW
Tape and reel SN74AHC02PWR
HA02
TVSOP – DGV Tape and reel SN74AHC02DGVR HA02
CDIP – J Tube SNJ54AHC02J SNJ54AHC02J
–55°C to 125°C
CFP – W Tube SNJ54AHC02W SNJ54AHC02W
LCCC – FK Tube SNJ54AHC02FK SNJ54AHC02FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54AHC02, SN74AHC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS254K– DECEMBER 1995 – REVISED JULY 2003
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A B
Y
H X L
X HL
L L H
logic diagram (positive logic)
2
1A
3
1B
1Y
1
8
3A
9
3B
3Y
10
5
2A
6
2B
2Y
4
11
4A
12
4B
4Y
13
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1) –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package 47°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
SN54AHC02, SN74AHC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS254K– DECEMBER 1995 – REVISED JULY 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54AHC02 SN74AHC02
UNIT
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 2 5.5 2 5.5 V
V
CC
= 2 V 1.5 1.5
V
IH
High-level input voltage
V
CC
= 3 V
2.1 2.1
V
V
CC
= 5.5 V 3.85 3.85
V
CC
= 2 V 0.5 0.5
V
IL
Low-level input voltage
V
CC
= 3 V
0.9 0.9
V
V
CC
= 5.5 V 1.65 1.65
V
I
Input voltage 0 5.5 0 5.5 V
V
O
Output voltage 0 V
CC
0 V
CC
V
V
CC
= 2 V –50 –50 A
I
OH
High-level output current
V
CC
= 3.3 V ± 0.3 V
–4 –4
mA
V
CC
= 5 V ± 0.5 V –8 –8
mA
V
CC
= 2 V 50 50 A
I
OL
Low-level output current
V
CC
= 3.3 V ± 0.3 V
4 4
mA
V
CC
= 5 V ± 0.5 V 8 8
mA
∆t/∆v
In
p
ut transition rise or fall rate
V
CC
= 3.3 V ± 0.3 V 100 100
ns/V
∆t/∆v
Input
transition
rise
or
fall
rate
V
CC
= 5 V ± 0.5 V 20 20
ns/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 4: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
T
A
= 25°C SN54AHC02 SN74AHC02
UNIT
PARAMETER
TEST
CONDITIONS
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 2 1.9 1.9
I
OH
= –50 A
3 V 2.9 3 2.9 2.9
V
OH
4.5 V 4.4 4.5 4.4 4.4
V
I
OH
= –4 mA 3 V 2.58 2.48 2.48
I
OH
= –8 mA 4.5 V 3.94 3.8 3.8
2 V 0.1 0.1 0.1
I
OL
= 50 A
3 V 0.1 0.1 0.1
V
OL
4.5 V 0.1 0.1 0.1
V
I
OL
= 4 mA 3 V 0.36 0.5 0.44
I
OL
= 8 mA 4.5 V 0.36 0.5 0.44
I
I
V
I
= 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1 A
I
CC
V
I
= V
CC
or GND, I
O
= 0 5.5 V 2 20 20 A
C
i
V
I
= V
CC
or GND 5 V 4 10 10 pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
CC
= 0 V.
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