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SN74ACT16245QDLREP

Part # SN74ACT16245QDLREP
Description IC BUS TRANSCVR 16BIT 48SSOP
Category IC
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

SN74ACT16245Q-EP
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS677A – MAY 2002 – REVISED JULY 2002
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
–40°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product Change Notification
Qualification Pedigree
Member of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
3-State Outputs Drive Bus Lines Directly
Flow-Through Architecture Optimizes PCB
Layout
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, highly
accelerated stress test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life.
description
The SN74ACT16245Q-EP is a 16-bit bus
transceiver organized as dual-octal noninverting
3-state transceivers and designed for
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
The device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on
the logic level at the direction-control (DIR) input. The enable (G
) input can be used to disable the devices so
that the buses are effectively isolated.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40°C to 125°C SSOP – DL Tape and reel SN74ACT16245QDLREP ACT16245QEP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
V
CC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CC
2B5
2B6
GND
2B7
2B8
2DIR
1G
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2G
SN74ACT16245Q-EP
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS677A MAY 2002 REVISED JULY 2002
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FUNCTION TABLE
(each section)
CONTROL
INPUTS
OPERATION
G DIR
L L B data to A bus
L H A data to B bus
H X Isolation
logic diagram (positive logic)
1DIR
1A1
1G
1B1
To Seven Other Transceivers
2DIR
2A1
2G
2B1
To Seven Other Transceivers
1
47
24
36
48
2
25
13
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) 0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1) 0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) ±24 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
) ±24 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±260 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
A
= 55°C (in still air) (see Note 2): DL package 1.2 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
SN74ACT16245Q-EP
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS677A MAY 2002 REVISED JULY 2002
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
Supply voltage (see Note 4) 4.5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
I
OH
High-level output current 16 mA
I
OL
Low-level output current 16 mA
t/v Input transition rise or fall rate 0 10 ns/V
T
A
Operating free-air temperature 40 125 °C
NOTES: 3. Unused inputs should be tied to V
CC
through a pullup resistor of approximately 5 k or greater to keep them from floating. Refer
to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4. All V
CC
and GND pins must be connected to the proper-voltage power supply.
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