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SN74ABT574AN

Part # SN74ABT574AN
Description OCTAL D-TYPE FLIP-FLOP
Category IC
Availability Out of Stock
Qty 0
Qty Price
1 + $0.18263



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

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  
SCBS191F − JANUARY 1991 − REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Typical V
OLP
(Output Ground Bounce)
<1 V at V
CC
= 5 V, T
A
= 25°C
D High-Drive Outputs (−32-mA I
OH
, 64-mA I
OL
)
D I
off
Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
SN54ABT574 ...J OR W PACKAGE
SN74ABT574A . . . DB, DW, N, NS,
OR PW PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
SN54ABT574...FK PACKAGE
(TOP VIEW)
2D
1D
OE
8Q
7Q 1Q
8D
GND
CLK
V
CC
SN74ABT574A . . . RGY PACKAGE
(TOP VIEW)
120
10 11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2D
3D
4D
5D
6D
7D
8D
CLK
V
G
ND
CC
OE
description/ordering information
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N Tube SN74ABT574AN SN74ABT574AN
QFN − RGY Tape and reel SN74ABT574ARGYR AB574A
SOIC − DW
Tube SN74ABT574ADW
ABT574A
SOIC − DW
Tape and reel SN74ABT574ADWR
ABT574A
−40°C to 85°C
SOP − NS Tape and reel SN74ABT574ANSR ABT574A
−40°C to 85°C
SSOP − DB Tape and reel SN74ABT574ADBR AB574A
TSSOP − PW
Tube SN74ABT574APW
AB574A
TSSOP − PW
Tape and reel SN74ABT574APWR
AB574A
VFBGA − GQN
Tape and reel
SN74ABT574AGQNR
AB574A
VFBGA − ZQN (Pb-free)
Tape and ree
l
SN74ABT574AZQNR
AB574A
CDIP − J Tube SNJ54ABT574J SNJ54ABT574J
−55°C to 125°C
CFP − W Tube SNJ54ABT574W SNJ54ABT574W
−55 C to 125 C
LCCC − FK Tube SNJ54ABT574FK SNJ54ABT574FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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  
SCBS191F − JANUARY 1991 − REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description/ordering information (continued)
The eight flip-flops of the SN54ABT574 and SN74ABT574A are edge-triggered D-type flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE
) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE
does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
terminal assignments
1234
A 1D OE V
CC
1Q
B 3D 3Q 2D 2Q
C 5D 4D 5Q 4Q
D 7D 7Q 6D 6Q
E GND 8D CLK 8Q
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE CLK D
OUTPUT
Q
L H H
L LL
L H or L X Q
0
H X X Z
logic diagram (positive logic)
OE
CLK
1D
1Q
To Seven Other Channels
C1
1
11
2
19
1D
Pin numbers shown are for the DB, DW, FK, J, N, NS, PW, RGY, and W packages.
SN74ABT574A . . . GQN OR ZQN PACKAGE
(TOP VIEW)
1234
A
B
C
D
E
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  
SCBS191F − JANUARY 1991 − REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
−0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
O
−0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
: SN54ABT574 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT574A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) −18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): GQN/ZQN package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package 37°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
SN54ABT574 SN74ABT574A
MIN MAX MIN MAX
V
CC
Supply voltage 4.5 5.5 4.5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 0 V
CC
0 V
CC
V
I
OH
High-level output current −24 −32 mA
I
OL
Low-level output current 48 64 mA
t/v Input transition rise or fall rate Outputs enabled 5 5 ns/V
T
A
Operating free-air temperature −55 125 −40 85 °C
NOTE 4: All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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