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FEATURES

DESCRIPTION

(TOP VIEW)

GND

SN65LVDS1

DBV Package

(TOP VIEW)

GND

SN65LVDS2 and SN65LVDT2

DBV Package

GND

SN65LVDS1

D Package

(TOP VIEW)

GND

SN65LVDS2 and SN65LVDT2

D Package

(TOP VIEW)

PART NUMBER

INTEGRATED

TERMINATION

PACKAGE

SOT23-5

PACKAGE

MARKING

SN65LVDS1DBV

SN65LVDS1D

SN65LVDS2DBV

SN65LVDS2D

SN65LVDT2DBV

SN65LVDT2D

√

SOIC-8

SAAI

LVDS1

SABI

LVDS2

SACI

LVDT2

AVAILABLE OPTIONS

SOT23-5

SOIC-8

110-Ω Resistor for LVDT Only

SN65LVDS1

SN65LVDS2

SN65LVDT2

SLLS373H – JULY 1999 – REVISED JULY 2006

HIGH-SPEED DIFFERENTIAL LINE DRIVER/RECEIVERS

• Meets or Exceeds the ANSI TIA/EIA-644A

Standard

• Designed for Signaling Rates

(1)

up to:

– 630 Mbps Drivers

– 400 Mbps Receivers

• Operates From a 2.4-V to 3.6-V Supply

• Available in SOT-23 and SOIC Packages

• Bus-Terminal ESD Exceeds 9 kV

• Low-Voltage Differential Signaling With

Typical Output Voltages of 350 mV Into a

100- Ω Load

• Propagation Delay Times

– 1.7 ns Typical Driver

– 2.5 ns Typical Receiver

• Power Dissipation at 200 MHz

– 25 mW Typical Driver

– 60 mW Typical Receiver

• LVDT Receiver Includes Line Termination

• Low Voltage TTL (LVTTL) Level Driver Input

Is 5-V Tolerant

• Driver Is Output High Impedance With

< 1.5 V

• Receiver Output and Inputs Are High

Impedance With V

< 1.5 V

• Receiver Open-Circuit Fail Safe

• Differential Input Voltage Threshold Less

Than 100 mV

The SN65LVDS1, SN65LVDS2, and SN65LVDT2

are single, low-voltage, differential line drivers and

receivers in the small-outline transistor package. The

outputs comply with the TIA/EIA-644A standard and

provide a minimum differential output voltage

magnitude of 247 mV into a 100- Ω load at signaling

rates up to 630 Mbps for drivers and 400 Mbps for

receivers.

(1) The signaling rate of a line is the number of voltage

transitions that are made per second expressed in the units

bps (bits per second)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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DESCRIPTION CONTINUED

INPUT OUTPUTS

Open

Y Z

DRIVER

INPUTS OUTPUT

= V

− V

≥ 100 mV

−100 mV < V

< 100 mV

≤ −100 mV

Open H

H = high level, L = low level , ? = indeterminate

RECEIVER

FUNCTION TABLES

DRIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

300 kΩ

50 Ω

7 V

D Input

5 Ω

10 kΩ

7 V

Y or Z

Output

RECEIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

7 V

R Output

5 Ω

A Input

300 kΩ300 kΩ

7 V

B Input

110-Ω LVDT Only

SN65LVDS1

SN65LVDS2

SN65LVDT2

SLLS373H – JULY 1999 – REVISED JULY 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

When the SN65LVDS1 is used with an LVDS receiver (such as the SN65LVDT2) in a point-to-point connection,

data or clocking signals can be transmitted over printed-circuit-board traces or cables at very high rates with

very low electromagnetic emissions and power consumption. The packaging, low power, low EMI, high ESD

tolerance, and wide supply voltage range make the device ideal for battery-powered applications.

The SN65LVDS1, SN65LVDS2, and SN65LVDT2 are characterized for operation from –40 ° C to 85 ° C.

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ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATING TABLE

RECOMMENDED OPERATING CONDITIONS

SN65LVDS1

SN65LVDS2

SN65LVDT2

SLLS373H – JULY 1999 – REVISED JULY 2006

over operating free-air temperature range (unless otherwise noted)

(1)

PARAMETER RATINGS

Supply voltage range, V

(2)

–0.5 V to 4 V

(A or B) –0.5 V to 4 V

Input voltage range, V

(D) –0.5 V to V

+ 2 V

Output voltage, V

(Y or Z) –0.5 V to 4 V

Differential input voltage

SN65LVDT2 only 1 V

magnitude, |V

Receiver output current, I

-12 mA to 12 mA

Human-body model electrostatic discharge, HBM ESD

(3)

All pins 4000 V

Bus pins (A, B, Y, Z) 9000 V

Machine-model electrostatic discharge, MM ESD

(4)

400 V

Field-induced-charge device model electrostatic discharge, FCDM ESD

(5)

1500 V

Continuous total power dissipation, P

See Dissipation Rating Table

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages are with respect to network ground terminal.

(3) Test method based upon JEDEC Standard 22, Test Method A114-A. Bus pins stressed with respect to GND and V

separately.

(4) Test method based upon JEDEC Standard 22, Test Method A114-A.

(5) Test method based upon EIA-JEDEC JESD22-C101C.

≤ 25 ° C DERATING FACTOR T

= 85 ° C

PACKAGE

POWER RATING ABOVE T

= 25 ° C

(1)

POWER RATING

D 725 mW 5.8 mW/ ° C 402 mW

DBV 385 mW 3.1 mW/ ° C 200 mW

(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-K) and with

no air flow.

PARAMETER MIN NOM MAX UNIT

Supply voltage 2.4 3.3 3.6 V

High-level input voltage 2 5 V

Low-level input voltage 0 0.8 V

Operating free-air temperature –40 85 ° C

| Magnitude of differential input voltage 0.1 0.6 V

Input voltage (any combination of input or common-mode voltage) 0 V

–0.8 V

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Part #	SN65LVDT2DBVT
Description	HIGH SPEED DIFFERENTIAL RECEIVER - Tape and Reel
Category	IC
Availability	Out of Stock
Qty	0

SN65LVDT2DBVT

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