SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Four (’391), Eight (’389) or Sixteen (’387)
Line Drivers Meet or Exceed the
Requirements of ANSI EIA/TIA-644
Standard
Designed for Signaling Rates
†
up to
630 Mbps With Very Low Radiation (EMI)
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100-Ω Load
Propagation Delay Times Less Than 2.9 ns
Output Skew Is Less Than 150 ps
Part-to-Part Skew Is Less Than 1.5 ns
35-mW Total Power Dissipation in Each
Driver Operating at 200 MHz
Driver Is High Impedance When Disabled or
With V
CC
< 1.5 V
SN65’ Version Bus-Pin ESD Protection
Exceeds 15 kV
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
Low-Voltage TTL (LVTTL) Logic Inputs Are
5-V Tolerant
description
This family of four, eight, and sixteen differential
line drivers implements the electrical characteris-
tics of low-voltage differential signaling (LVDS).
This signaling technique lowers the output voltage
levels of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a
3.3-V supply rail. Any of the sixteen current-mode
drivers will deliver a minimum differential output
voltage magnitude of 247 mV into a 100-Ω load
when enabled.
The intended application of this device and signaling technique is for point-to-point and multidrop baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media can be
printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same
substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of
clock and data for synchronous parallel data transfers. When used with the companion 16- or 8-channel
receivers, the SN65LVDS386 or SN65LVDS388, over 300 million data transfers per second in single-edge
clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
system characteristics.)
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
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GND
V
CC
V
CC
GND
ENA
A1A
A2A
A3A
A4A
ENB
B1A
B2A
B3A
B4A
GND
V
CC
V
CC
GND
C1A
C2A
C3A
C4A
ENC
D1A
D2A
D3A
D4A
END
GND
V
CC
V
CC
GND
A1Y
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
C1Y
C1Z
C2Y
C2Z
C3Y
C3Z
C4Y
C4Z
D1Y
D1Z
D2Y
D2Z
D3Y
D3Z
D4Y
D4Z
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5
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35
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GND
V
CC
GND
ENA
A1A
A2A
A3A
A4A
GND
V
CC
GND
B1A
B2A
B3A
B4A
ENB
GND
V
CC
GND
A1Y
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
NC
NC
NC
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
’LVDS389
DBT PACKAGE
(TOP VIEW)
’LVDS387
DGG PACKAGE
(TOP VIEW)
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3
4
5
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7
8
16
15
14
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10
9
EN1,2
1A
2A
V
CC
GND
3A
4A
EN3,4
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
’LVDS391
D OR PW PACKAGE
(TOP VIEW)
