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SN65LVDS150PW

Part # SN65LVDS150PW
Description PLL WITH LVDS I/O - Rail/Tube
Category IC
Availability In Stock
Qty 10
Qty Price
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3 - 4 $6.60017
5 - 6 $6.22302
7 - 8 $5.78301
9 + $5.15442
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Texas Instruments
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

SN65LVDS150
MuxIt PLL FREQUENCY MULTIPLIER
SLLS443 – DECEMBER 2000
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
A Member of the MuxIt Serializer-
Deserializer Building-Block Chip Family
Pin Selectable Frequency Multiplier Ratios
Between 4 and 40
Input Clock Frequencies From 5 to 50 MHz
Multiplied Clock Frequencies up to
400 MHz
Internal Loop Filters and Low PLL-Jitter of
20 ps RMS Typical at 200 MHz
LVDS Compatible Differential Inputs and
Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644-A
LVTTL Compatible Inputs Are 5 V Tolerant
LVDS Inputs and Outputs ESD Protection
Exceeds 12 kV HBM
Operates From a Single 3.3 V Supply
Packaged in 28-Pin Thin Shrink
Small-Outline Package With 26 mil Terminal
Pitch
description
The MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers
and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of
differential transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or
LVCMOS) data interface. The number of bits multiplexed per transmission line is user selectable, allowing for
higher transmission efficiencies than with other existing fixed ratio solutions. Muxlt utilizes the LVDS
(TIA/EIA-644) low voltage differential signaling technology for communications between the data source and
data destination.
The MuxIt family initially includes three devices supporting simplex communications;
The SN65LVDS150
Phase Locked Loop-Frequency Multiplier, The SN65LVDS151 Serializer-Transmitter,
and
The SN65LVDS152
Receiver-Deserializer.
The SN65LVDS150 is a PLL based frequency multiplier designed for use with the other members of the MuxIt
family of serializers and deserializers. The frequency multiplication ratio is pin selectable over a wide range of
values from 4 through 40 to accommodate a broad spectrum of user needs. No external filter components are
needed. A PLL lock indicator output is available which may be used to enable link data transfers.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
CRI+
CRI–
V
T
GND
M1
M2
M3
M4
M5
BSEL
GND
LCRO–
LCRO+
NC
NC
NC
V
CC
GND
NC
GND
NC
MCO+
MCO–
GND
EN
LCRO_EN
LVO
SN65LVDS150
PW PACKAGE
(Marked as 65LVDS150)
NC – No internal connection
Muxlt is a trademark of Texas Instruments.
SN65LVDS150
MuxIt PLL FREQUENCY MULTIPLIER
SLLS443 – DECEMBER 2000
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
The design of the SN65LVDS150 allows it to be used at either the transmit end or the receive end of the MuxIt
serial link. The differential clock reference input (CRI) is driven by the system’s parallel data clock when at the
source end of the link, or by the link clock when at the destination end of the link. The differential clock reference
input may be driven by either an LVDS differential signal, or by a single ended clock of either polarity. For
single-ended use the nonclocked input is biased to the logic threshold voltage. A V
CC
/2 threshold reference,
VT, is provided on a pin adjacent the differential CRI pins for convenience when the input is used in a
single-ended mode.
The multiplied clock output (MCO) is an LVDS differential signal used to drive the high-speed shift registers in
either the SN65LVDS151 serializer-transmitter or the SN65LVDS152 receiver-deserializer. The link clock
reference output (LCRO) is an LVDS differential signal provided to the SN65LVDS151 serializer-transmitter for
transmission over the link.
An internal power on reset and an enable input (EN) control the operation of the SN65LVDS150. When V
CC
is
below 1.5 V, or when EN is low, the device is in a low power disabled state and the MCO and LCRO differential
outputs are in a high-impedance state. When V
CC
is above 3 V and EN is high, the device and the two differential
outputs are enabled and operating to specifications. The link clock reference output enable input (LCRO_EN)
is used to turn off the LCRO output when it is not being used. A band select input (BSEL) is used to optimize
the VCO performance as a function of M-clock frequencies and M multiplier that is being used: The f
max
parameter in the switching characteristic table includes details on the MCO frequency and choices of BSEL and
M.
block diagram
Frequency
Phase
Detector
VCO
Divide by M
M1 M2 M3 M4 M5
LVO
MCO+
MCO–
LCRO+
LCRO–
CRI+
CRI–
BSEL
EN
LCRO_EN
Ref.
Gen.
VT
SN65LVDS150
MuxIt PLL FREQUENCY MULTIPLIER
SLLS443 – DECEMBER 2000
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
frequency multiplier value table
MULTIPLIER
M1
M2
M3
M4
M5
RECOMMENDED f
IN
(MHz)
(m)
M1
M2
M3
M4
M5
BSEL = 0 BSEL = 1
4 L L L L L f
IN
< 12.50 12.50 f
IN
L L L L H NA NA
6 L L L H L f
IN
< 8.33 8.33 f
IN
L L L H H NA NA
8 L L H L L f
IN
< 12.50 12.50 f
IN
9 L L H L H f
IN
< 11.11 11.11 f
IN
10 L L H H L f
IN
< 10.00 10.00 f
IN
L L H H H NA NA
12 L H L L L f
IN
< 8.3 8.3 f
IN
13 L H L L H f
IN
< 7.7 7.7 f
IN
14 L H L H L f
IN
< 7.14 7.14 f
IN
15 L H L H H f
IN
< 6.67 6.67 f
IN
16 L H H L L f
IN
< 6.25 6.25 f
IN
17 L H H L H f
IN
< 5.88 5.88 f
IN
18 L H H H L f
IN
< 5.56 5.56 f
IN
19 L H H H H f
IN
< 5.26 5.26 f
IN
20 H L L L L f
IN
= 5.00 5.00 f
IN
22 H L L L H NA 5.00 f
IN
24 H L L H L NA 5.00 f
IN
26 H L L H H NA 5.00 f
IN
28 H L H L L NA 5.00 f
IN
30 H L H L H NA 5.00 f
IN
32 H L H H L NA 5.00 f
IN
34 H L H H H NA 5.00 f
IN
36 H H L L L NA 5.00 f
IN
38 H H L L H NA 5.00 f
IN
40 H H L H L NA 5.00 f
IN
H H L H H NA NA
H H H L L NA NA
H H H L H NA NA
H H H H L NA NA
H H H H H NA NA
H = high level, L= low level † = Reserved
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