NOTES:
t
n
= bit time before enable
negative-going transition
t
n+1
= bit time after enable
negative-going transition
5-75
FAST AND LS TTL DATA
4-BIT D LATCH
The TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem-
porary storage for binary information between processing units and input/out-
put or indicator units. Information present at a data (D) input is transferred to
the Q output when the Enable is HIGH and the Q output will follow the data
input as long as the Enable remains HIGH. When the Enable goes LOW, the
information (that was present at the data input at the time the transition oc-
curred) is retained at the Q output until the Enable is permitted to go HIGH.
The SN54/74LS75 features complementary Q and Q
output from a 4-bit
latch and is available in the 16-pin packages. For higher component density
applications the SN54/74LS77 4-bit latch is available in the 14-pin package
with Q
outputs omitted.
14 13 12 11 10 9
1 2 3 4 5 6
7
16 15
8
CONNECTION DIAGRAMS DIP (TOP VIEW)
SN54/74LS75
14 13 12 11 10 9
1 2 3 4 5 6
8
7
SN54/74LS77
Q
0
Q
0
Q
1
Q
1
E
0–1
GND Q
2
Q
2
Q
3
D
0
D
1
E
2–3
V
CC
D
2
D
3
Q
3
Q
0
Q
1
E
0–1
GND NC Q
2
Q
3
D
0
D
1
E
2–3
V
CC
D
2
D
3
NC
PIN NAMES LOADING (Note a)
HIGH
LOW
D
1
–D
4
E
0–1
E
2–3
Q
1
–Q
4
Q
1
–Q
4
Data Inputs
Enable Input Latches 0, 1
Enable Input Latches 2, 3
Latch Outputs (Note b)
Complimentary Latch Outputs (Note b)
0.5 U.L.
2.0 U.L.
2.0 U.L.
10 U.L.
10 U.L.
0.25 U.L.
1.0 U.L.
1.0 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a) 1 Unit Load (U.L.) = 40 µA HIGH.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
TRUTH TABLE
(Each latch)
t
n
t
n+1
D
H
L
Q
H
L
SN54/74LS75
SN54/74LS77
4-BIT D LATCH
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14
1
14
1
14
1
D SUFFIX
SOIC
CASE 751A-02
