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SN54LS164J

Part # SN54LS164J
Description 8-BIT SHIFT REGISTER - Rail/Tube
Category IC
Availability In Stock
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

5-1
FAST AND LS TTL DATA
SERIAL-IN PARALLEL-OUT
SHIFT REGISTER
The SN54/74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift Regis-
ter. Serial data is entered through a 2-Input AND gate synchronous with the
LOW to HIGH transition of the clock. The device features an asynchronous
Master Reset which clears the register setting all outputs LOW independent of
the clock. It utilizes the Schottky diode clamped process to achieve high
speeds and is fully compatible with all Motorola TTL products.
Typical Shift Frequency of 35 MHz
Asynchronous Master Reset
Gated Serial Data Input
Fully Synchronous Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
14 13 12 11 10 9
1 2 3 4 5 6
8
7
V
CC
Q
7
Q
6
Q
5
Q
4
MR
CP
A B Q
0
Q
1
Q
2
Q
3
GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
PIN NAMES LOADING (Note a)
HIGH
LOW
A, B
CP
MR
Q
0
Q
7
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
SN54/74LS164
SERIAL-IN PARALLEL-OUT
SHIFT REGISTER
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14
1
14
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
14
1
D SUFFIX
SOIC
CASE 751A-02
LOGIC SYMBOL
1
2
8
9 3 4 5 6 10 11 12 13
A
B
CP
LS164
8-BIT SHIFT REGISTER
MR Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
V
CC
= PIN 14
GND = PIN 7
5-2
FAST AND LS TTL DATA
SN54/74LS164
LOGIC DIAGRAM
Q
6
Q
7
A
B
Q
0
Q
1
Q
3
Q
2
Q
5
Q
4
MR
CP
D Q
C
D
D Q
C
D
D Q
C
D
D Q
C
D
D Q
C
D
D Q
C
D
D Q
C
D
D Q
C
D
63 4 5 11 1210 13
V
CC
= PIN 14
GND = PIN 7
= PIN NUMBERS
1
2
8
9
FUNCTIONAL DESCRIPTION
The LS164 is an edge-triggered 8-bit shift register with seri-
al data entry and an output from each of the eight stages. Data
is entered serially through one of two inputs (A or B); either of
these inputs can be used as an active HIGH Enable for data
entry through the other input. An unused input must be tied
HIGH, or both inputs connected together.
Each LOW-to-HIGH transition on the Clock (CP) input shifts
data one place to the right and enters into Q
0
the logical AND
of the two data inputs (AB) that existed before the rising clock
edge. A LOW level on the Master Reset (MR
) input overrides
all other inputs and clears the register asynchronously, forcing
all Q outputs LOW.
MODE SELECT — TRUTH TABLE
OPERATING
MODE
INPUTS OUTPUTS
MODE
MR A B Q
0
Q
1
–Q
7
Reset (Clear) L X X L L – L
H I I L q
0
– q
6
Shift H I h L q
0
– q
6
H h I L q
0
– q
6
H h h H q
0
– q
6
L (l) = LOW Voltage Levels
H (h) = HIGH Voltage Levels
X = Don’t Care
q
n
= Lower case letters indicate the state of the referenced input or output one
q
n
= set-up time prior to the LOW to HIGH clock transition.
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range 54
74
55
0
25
25
125
70
°C
I
OH
Output Current — High 54, 74 0.4 mA
I
OL
Output Current — Low 54
74
4.0
8.0
mA
5-3
FAST AND LS TTL DATA
SN54/74LS164
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
V
IH
Input HIGH Voltage 2.0 V
Guaranteed Input HIGH Voltage for
All Inputs
V
IL
Input LOW Voltage
54 0.7
V
Guaranteed Input LOW Voltage for
All Inputs
V
IL
Input LOW Voltage
74 0.8
V
Guaranteed Input LOW Voltage for
All Inputs
V
IK
Input Clamp Diode Voltage 0.65 1.5 V V
CC
= MIN, I
IN
= –18 mA
V
OH
Output HIGH Voltage
54 2.5 3.5
V
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
V
OH
Output HIGH Voltage
74 2.7 3.5
V
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
V
OL
Output LOW Voltage
54, 74 0.25 0.4 V I
OL
= 4.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IH
or V
IL
per Truth Table
V
OL
Output LOW Voltage
74 0.35 0.5 V I
OL
= 8.0 mA
V
IN
= V
IH
or V
IL
per Truth Table
I
IH
Input HIGH Current
20 µA V
CC
= MAX, V
IN
= 2.7 V
I
IH
Input HIGH Current
0.1 mA V
CC
= MAX, V
IN
= 7.0 V
I
IL
Input LOW Current 0.4 mA V
CC
= MAX, V
IN
= 0.4 V
I
OS
Short Circuit Current (Note 1) 20 –100 mA V
CC
= MAX
I
CC
Power Supply Current 27 mA V
CC
= MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T
A
= 25°C)
Parameter
Limits
Unit
Test Conditions
Parameter
Min Typ Max
Unit
Test Conditions
f
MAX
Maximum Clock Frequency 25 36
MHz
V
CC
= 5.0 V
C
L
= 15 pF
t
PHL
Propagation Delay
MR
to Output Q
24 36 ns
V
CC
= 5.0 V
C
L
= 15 pF
t
PLH
t
PHL
Propagation Delay
Clock to Output Q
17
21
27
32
ns
C
L
= 15 pF
AC SETUP REQUIREMENTS (T
A
= 25°C)
Parameter
Limits
Unit
Test Conditions
Parameter
Min Typ Max
Unit
Test Conditions
t
W
CP, MR Pulse Width 20
ns
V
CC
= 5.0 V
t
s
Data Setup Time 15
ns
V
CC
= 5.0 V
t
h
Data Hold Time 5.0
ns
V
CC
= 5.0 V
t
rec
MR to Clock Recovery Time 20
ns
12NEXT