Si5326
Rev. 1.0 19
The Si5326 has two differential clock outputs. The
electrical format of each clock output is independently
programmable to support LVPECL, LVDS, CML, or
CMOS loads. If not required, the second clock output
can be powered down to minimize power consumption.
The phase difference between the selected input clock
and the output clocks is adjustable in 200 ps increments
for system skew control using the CLAT
[7:0] register.
Fine phase adjustment is available and is set using the
FLAT
register bits. The nominal range and resolution of
the FLAT
[14:0] skew adjustment word are: ±110 ps and
3 ps, respectively. In addition, the phase of one output
clock may be adjusted in relation to the phase of the
other output clock. The resolution varies from 800 ps to
2.2 ns depending on the PLL divider settings. See
Tab le 8 for instructions on ensuring output-to-output
alignment. The input to output skew is not specified.
The DSPLLsim software utility determines the phase
offset resolution for a given input clock/clock
multiplication ratio combination. For system-level
debugging, a bypass mode is available which drives the
output clock directly from the input clock, bypassing the
internal DSPLL. The device is powered by a single 1.8,
2.5, or 3.3 V supply.
4.1. External Reference
An external, high quality clock or a low-cost
114.285 MHz 3rd overtone crystal is used as part of a
fixed-frequency oscillator within the DSPLL. This
external reference is required for the device to perform
jitter attenuation. Silicon Laboratories recommends
using a high quality crystal. Specific recommendations
may be found in the Family Reference Manual.
In digital hold, the DSPLL remains locked and tracks the
external reference. Note that crystals can have
temperature sensitivities.
4.2. Further Documentation
Consult the Silicon Laboratories Si53xx Any Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5326 functions.
Additional design support is available from Silicon
Laboratories through your distributor.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing.
Table 8. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table
CKOUT_ALWAYS_ON SQ_ICAL Results
0 0 CKOUT OFF until after the first ICAL
0 1 CKOUT OFF until after the first successful
ICAL (i.e., when LOL is low)
1 0 CKOUT always ON, including during an ICAL
1 1 CKOUT always ON, including during an ICAL.
Use these settings to preserve output-to-output
skew
