Si5326
8 Rev. 1.0
3-Level Input Pins
4
Input Voltage Low V
ILL
— — 0.15 x V
DD
V
Input Voltage Mid V
IMM
0.45 x
V
DD
—0.55xV
DD
V
Input Voltage High V
IHH
0.85 x
V
DD
——V
Input Low Current I
ILL
See Note 4 –20 — — µA
Input Mid Current I
IMM
See Note 4 –2 — +2 µA
Input High Current I
IHH
See Note 4 — — 20 µA
LVCMOS Output Pins
Output Voltage Low V
OL
IO = 2 mA
V
DD
=1.71V
—— 0.4 V
Output Voltage Low IO = 2 mA
V
DD
=2.97V
—— 0.4 V
Output Voltage High V
OH
IO = –2 mA
V
DD
=1.71V
V
DD
–
0.4
——V
Output Voltage High IO = –2 mA
V
DD
=2.97V
V
DD
–
0.4
——V
Disabled Leakage
Current
I
OZ
RSTb = 0 –100 — 100 µA
Table 2. DC Characteristics (Continued)
(V
DD
= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1.
Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal V
DD
≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx
Family Reference Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
