Rev. 1.0 9/10 Copyright © 2010 by Silicon Laboratories Si5326
Si5326
ANY FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER
A
TTENUATOR
Features
Applications
Description
The Si5326 is a jitter-attenuating precision clock multiplier for applications
requiring sub 1 ps jitter performance. The Si5326 accepts two input clocks ranging
from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to
945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down
separately from a common source. The Si5326 can also use its crystal oscillator
as a clock source for frequency synthesis. The device provides virtually any
frequency translation combination across this operating range. The Si5326 input
clock frequency and clock multiplication ratio are programmable through an I
2
C or
SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation
DSPLL
®
technology, which provides frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need for external VCXO and
loop filter components. The DSPLL loop bandwidth is digitally programmable,
providing jitter performance optimization at the application level. Operating from a
single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock
multiplication and jitter attenuation in high performance timing applications.
Generates any frequency from 2 kHz
to 945 MHz and select frequencies to
1.4 GHz from an input frequency of
2 kHz to 710 MHz
Ultra-low jitter clock outputs with jitter
generation as low as 0.3 ps rms
(50 kHz–80 MHz)
Integrated loop filter with selectable
loop bandwidth (60 Hz to 8.4 kHz)
Meets OC-192 GR-253-CORE jitter
specifications
Dual clock inputs with manual or
automatically controlled hitless
switching (LVPECL, LVDS, CML,
CMOS)
Dual clock outputs with selectable
signal format
Support for ITU G.709 and custom
FEC ratios (255/238, 255/237,
255/236)
LOL, LOS, FOS alarm outputs
Digitally-controlled output phase
adjustment
I
2
C or SPI programmable
On-chip voltage regulator for
1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%
operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant
SONET/SDH OC-48/OC-192/STM-
16/STM-64 line cards
ITU G.709 and custom FEC line
cards
GbE/10GbE, 1/2/4/8/10G Fibre
Channel line cards
GbE/10GbE Synchronous Ethernet
Optical modules
Wireless basestations
Data converter clocking
xDSL
PDH clock synthesis
Test and measurement
Broadcast video
Ordering Information:
See page 65.
Pin Assignments
1
2
3
2930313233343536
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
NC
NC
RST
C2B
INT_C1B
GND
VDD
XA
VDD
RATE0
CKIN2+
CKIN2–
NC
RATE1
CKIN1+
CKIN1–
CS_CA
SCL
SDA_SDO
A1
A2_SS
SDI
CKOUT1–
NC
GND
VDD
NC
CKOUT2–
CKOUT2+
CMODE
GND
Pad
A0
INC
9
18
19
28
XB
LOL
DEC
CKOUT1+
