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S29GL256N10TFI020

Part # S29GL256N10TFI020
Description NOR Flash Parallel 3.3V 256M-bit 32M x 8/16M x 16 100ns 56
Category IC
Availability In Stock
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Date Code: 0623
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

May 13, 2004 27631A4 S29GLxxxN MirrorBitTM Flash Family 109
Advance Information
Revision A+4 (May 13, 2004)
Global
Removed references to RTSOP.
Distinctive Characteristics
Removed 16-word/32-byte page read buffer from Performance Characteristics.
Changed Low power consumption to 25 mA typical active read current and re-
moved 10 mA typical intrapage active read current.
Ordering Information
Changed formatting of pages.
Changed model numbers from 00,01,02,03 to 01, 02, V1, V2.
Table 1, “Device Bus Operations
Combined WP# and ACC columns.
Table 8, “CFI Query Identification String”, Table 9, “System Interface
String”, Table 10, “Device Geometry Definition”, and Table 11, “Primary
Vendor-Specific Extended Query
Added Address (x8) column.
Word Program Command Sequence
Added text to fourth paragraph.
Figure 1, “Write Buffer Programming Operation,”
Added note references and removed DQ15 and DQ13.
Figure 3, “Program Suspend/Program Resume,”
Changed field to read XXXh/B0h and XXXh/30h.
Password Protection Command Set Definitions
Replaced all text.
Table 12, “S29GL512N, S29GL256N, S29GL128N Command Definitions,
x16
Changed the first cycle address of CFI Query to 55.
Table 13, “S29GL512N, S29GL256N, S29GL128N Command Definitions,
x8
Changed the third cycle data Device ID to 90.
Removed Unlock Bypass Reset.
Removed Note 12 and 13.
Figure 5, “Data# Polling Algorithm,
Removed DQ15 and DQ13.
Absoulte Maximum Ratings
Removed VCC from “All other pins” with respect to Ground.
CMOS Compatible
Changed the Max of I
CC4
to 70 mA
Added V
IL
to the Test conditions of I
CC5
, I
CC6
, and I
CC7
Change the Min of V
IL
to - 0.1 V.
Updated note 5.
Read-Only Operations–S29GL128N Only
Added t
CEH
parameter to table.
110 S29GLxxxN MirrorBitTM Flash Family 27631A4 May 13, 2004
Advance Information
Figure 11, “Read Operation Timings,”
Added t
CEH
to figure.
Figure 12, “Page Read Timings,”
Change A1-A0 to A2-A0.
Erase and Program Operations
Updated t
WHWH1
and t
WHWH2
with values.
Figure 16, “Chip/Sector Erase Operation Timings,”
Changed 5555h to 55h and 3030h to 30h.
Figure 17, “Data# Polling Timings (During Embedded Algorithms),”
Removed DQ15 and DQ14-DQ8
Added Note 2
Figure 18, “Toggle Bit Timings (During Embedded Algorithms),”
Changed DQ6 & DQ14/DQ2 & DQ10 to DQ2 and DQ6.
Alternate CE# Controlled Erase and Program Operations
Updated t
WHWH1
and t
WHWH2
with values.
Latchup Characteristics
Removed Table.
Erase and Programming Performance
Updated TBD with values.
Updated Note 1 and 2.
Physical Dimensions
Removed the reverse pinout information and note 3.
Trademarks and Notice
The contents of this document are subject to change without notice.
This document may contain information on a Spansion product under development by FASL LLC. FASL LLC reserves the right to change or discontinue work
on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness,
operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. FASL
LLC assumes no liability for any damages of any kind arising out of the use of the information in this document.
Copyright © 2004 FASL LLC. All rights reserved.
Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of FASL LLC. Other company and product names used in this
publication are for identification purposes only and may be trademarks of their respective companies.
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