94 S29GLxxxN MirrorBitTM Flash Family 27631A4 May 13, 2004
Advance Information
AC Characteristics
Erase and Program Operations–S29GL256N Only
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
3. For 1–16 words/1–32 bytes programmed.
4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.
5. Unless otherwise indicated, AC specifications for 80 ns and 90 ns speed options are tested with V
IO
= V
CC
= 3 V.
AC specifications for 90 ns and 100 ns speed options are tested with V
IO
= 1.8 V and V
CC
= 3.0 V.
Parameter Speed Options
JEDEC Std.
Description
80 90 90 100 Unit
t
AVAV
t
WC
Write Cycle Time (Note 1) Min 80 90 90 100 ns
t
AVWL
t
AS
Address Setup Time Min 0 ns
t
ASO
Address Setup Time to OE# low during toggle
bit polling
Min 15 ns
t
WLAX
t
AH
Address Hold Time Min 45 ns
t
AHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min 0 ns
t
DVWH
t
DS
Data Setup Time Min 45 ns
t
WHDX
t
DH
Data Hold Time Min 0 ns
t
OEPH
Output Enable High during toggle bit polling Min 20 ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min 0 ns
t
ELWL
t
CS
CE# Setup Time Min 0 ns
t
WHEH
t
CH
CE# Hold Time Min 0 ns
t
WLWH
t
WP
Write Pulse Width Min 35 ns
t
WHDL
t
WPH
Write Pulse Width High Min 30 ns
t
WHWH1
t
WHWH1
Write Buffer Program Operation (Notes 2, 3) Typ 240 µs
Effective Write Buffer Program
Operation (Notes 2, 4)
Per Word Typ 15 µs
Accelerated Effective Write Buffer
Program Operation (Notes 2, 4)
Per Word Typ 13.5 µs
Program Operation (Note 2) Word Typ 60 µs
Accelerated Programming
Operation (Note 2)
Word Typ 54 µs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2) Typ 1.0 sec
t
VHH
V
HH
Rise and Fall Time (Note 1) Min 250 ns
t
VCS
V
CC
Setup Time (Note 1) Min 50 µs
