May 13, 2004 27631A4 S29GLxxxN MirrorBitTM Flash Family 79

Advance Information

gram address falls within a protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to the read mode.

During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.

When the Embedded Erase algorithm is complete, or if the device enters the

Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must

provide an address within any of the sectors selected for erasure to read valid

status information on DQ7.

After an erase command sequence is written, if all sectors selected for erasing

are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the

device returns to the read mode. If not all selected sectors are protected, the Em-

bedded Erase algorithm erases the unprotected sectors, and ignores the selected

sectors that are protected. However, if the system reads DQ7 at an address within

a protected sector, the status may not be valid.

Just prior to the completion of an Embedded Program or Erase operation, DQ7

may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is as-

serted low. That is, the device may change from providing status information to

valid data on DQ7. Depending on when the system samples the DQ7 output, it

may read the status or valid data. Even if the device has completed the program

or erase operation and DQ7 has valid data, the data outputs on DQ0–DQ6 may

be still invalid. Valid data on DQ0–DQ7 will appear on successive read cycles.

Table 14 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data#

Polling algorithm. Figure 17 in the AC Characteristics section shows the Data#

Polling timing diagram.

80 S29GLxxxN MirrorBitTM Flash Family 27631A4 May 13, 2004

Advance Information

Figure 5. Data# Polling Algorithm

RY/BY # : Read y/Busy#

The RY/BY# is a dedicated, open-drain output pin which indicates whether an

Embedded Algorithm is in progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command sequence. Since RY/BY#

is an open-drain output, several RY/BY# pins can be tied together in parallel with

a pull-up resistor to V

If the output is low (Busy), the device is actively erasing or programming. (This

includes programming in the Erase Suspend mode.) If the output is high (Ready),

the device is in the read mode, the standby mode, or in the erase-suspend-read

mode. Table 14 shows the outputs for RY/BY#.

DQ7 = Data?

Yes

DQ5 = 1

Yes

FAIL

PASS

Read DQ15–DQ0

Addr = VA

Read DQ15–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

May 13, 2004 27631A4 S29GLxxxN MirrorBitTM Flash Family 81

Advance Information

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm

is in progress or complete, or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is valid after the rising edge

of the final WE# pulse in the command sequence (prior to the program or erase

operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cy-

cles to any address cause DQ6 to toggle. The system may use either OE# or CE#

to control the read cycles. When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing

are protected, DQ6 toggles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the selected sectors that are

protected.

The system can use DQ6 and DQ2 together to determine whether a sector is ac-

tively erasing or is erase-suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-

ters the Erase Suspend mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-

natively, the system can use DQ7 (see the subsection on DQ7: Data# Polling).

If a program address falls within a protected sector, DQ6 toggles for approxi-

mately 1 µs after the program command sequence is written, then returns to

reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling

once the Embedded Program algorithm is complete.

Table 14 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit

algorithm. Figure 18 in the “AC Characteristics” section shows the toggle bit tim-

ing diagrams. Figure 19 shows the differences between DQ2 and DQ6 in graphical

form. See also the subsection on DQ2: Toggle Bit II.

Part #	S29GL256N10TFI020
Description	NOR Flash Parallel 3.3V 256M-bit 32M x 8/16M x 16 100ns 56
Category	IC
Availability	In Stock
Qty	2

S29GL256N10TFI020

Related Items

Technical Document