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S29GL256N10TFI020

Part # S29GL256N10TFI020
Description NOR Flash Parallel 3.3V 256M-bit 32M x 8/16M x 16 100ns 56
Category IC
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Date Code: 0623
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

May 13, 2004 27631A4 S29GLxxxN MirrorBitTM Flash Family 55
Advance Information
Ta b l e 8 . CFI Query Identification String
Table 9. System Interface String
Addresses
(x16)
Addresses
(x8) Data Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Addresses
(x16)
Addresses
(x8) Data Description
1Bh 36h 0027h
V
CC
Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 38h 0036h
V
CC
Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh 3Ah 0000h V
PP
Min. voltage (00h = no V
PP
pin present)
1Eh 3Ch 0000h V
PP
Max. voltage (00h = no V
PP
pin present)
1Fh 3Eh 0007h Typical timeout per single byte/word write 2
N
µs
20h 40h 0007h Typical timeout for Min. size buffer write 2
N
µ
s (00h = not supported)
21h 42h 000Ah Typical timeout per individual block erase 2
N
ms
22h 44h 0000h Typical timeout for full chip erase 2
N
ms (00h = not supported)
23h 46h 0001h Max. timeout for byte/word write 2
N
times typical
24h 48h 0005h Max. timeout for buffer write 2
N
times typical
25h 4Ah 0004h Max. timeout per individual block erase 2
N
times typical
26h 4Ch 0000h Max. timeout for full chip erase 2
N
times typical (00h = not supported)
56 S29GLxxxN MirrorBitTM Flash Family 27631A4 May 13, 2004
Advance Information
Ta b l e 1 0 . Device Geometry Definition
Addresses
(x16)
Addresses
(x8) Data Description
27h 4Eh
001Ah
0019h
0018h
Device Size = 2
N
byte
1A = 512 Mb, 19 = 256 Mb, 18 = 128 Mb
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0005h
0000h
Max. number of byte in multi-byte write = 2
N
(00h = not supported)
2Ch 58h 0001h
Number of Erase Block Regions within device (01h = uniform device,
02h = boot device)
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
00xxh
000xh
0000h
000xh
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
00FFh, 001h, 0000h, 0002h = 512 Mb
00FFh, 0000h, 0000h, 0002h = 256 Mb
007Fh, 0000h, 0000h, 0002h = 128 Mb
31h
32h
33h
34h
60h
64h
66h
68h
0000h
0000h
0000h
0000h
Erase Block Region 2 Information (refer to CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information (refer to CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information (refer to CFI publication 100)
May 13, 2004 27631A4 S29GLxxxN MirrorBitTM Flash Family 57
Advance Information
Ta b l e 1 1 . Primary Vendor-Specific Extended Query
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 12 and Table 13 define the valid register
command sequences. Writing incorrect address and data values or writing them
in the improper sequence may place the device in an unknown state. A reset com-
mand is then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing diagrams.
Addresses
(x16)
Addresses
(x8) Data Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI
43h 86h 0031h Major version number, ASCII
44h 88h 0033h Minor version number, ASCII
45h 8Ah 0010h
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Process Technology (Bits 7-2) 0100b = 110 nm MirrorBit
46h 8Ch 0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 8Eh 0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h 90h 0000h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 92h 0008h
Sector Protect/Unprotect scheme
0008h = Advanced Sector Protection
4Ah 94h 0000h
Simultaneous Operation
00 = Not Supported, X = Number of Sectors in Bank
4Bh 96h 0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch 98h 0002h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh 9Ah 00B5h
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Eh 9Ch 00C5h
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh 9Eh 00xxh
WP# Protection
04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors
top WP# protect
50h A0h 0001h
Program Suspend
00h = Not Supported, 01h = Supported
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